Variable Latency Phase Change Memory Control
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Solution Overview
Problem
Conventional phase change memory (PCM) devices face limitations in write and read operations, where write operations are slower and cannot be performed simultaneously with read operations, restricting their usage in memory systems due to variable latency issues.
Innovation Solution
Implementing a three-phase addressing mechanism with a variable latency period (tLAT) that allows for managing memory operations, including suspending or completing current operations, and prioritizing commands by adjusting tMAXLATR and tMAXLATW values stored in registers, enabling read and write operations to be performed after the latency period elapses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCM is used to implement random access memory, then non-volatile memory capability is achieved, but write operations become slower and cannot be performed simultaneously with read operations
Solution Approach 1:
The patent implements dynamic latency periods (tLAT) that vary based on operation type and priority. Write operations are assigned longer latency periods to accommodate their slower speed, while read operations use shorter latency periods. This dynamic adjustment allows the memory system to optimize performance for each operation type, resolving the contradiction between maintaining non-volatile capabilities and achieving high write speeds.
Solution Approach 2:
The patent segments memory operations into distinct phases with different latency requirements. By dividing the memory access timeline into separate latency periods for reads and writes, and further segmenting based on priority levels, the system can manage simultaneous operations more effectively. This segmentation allows write operations to proceed without being blocked by read operations, improving write throughput while maintaining reliability.
2Reliability
If status registers are queried to monitor write operation progress, then operation completion can be determined, but system complexity increases and operation flexibility decreases
Solution Approach 1:
The patent implements feedback mechanisms where the memory device automatically provides completion status information to the controller. Instead of requiring the controller to continuously query status registers, the memory device feeds back completion information proactively, reducing the complexity of monitoring while ensuring reliable operation completion detection.
Solution Approach 2:
The memory system performs self-monitoring of operation completion through integrated status tracking within the memory device itself. This self-service approach eliminates the need for external polling mechanisms, reducing system complexity while maintaining reliable monitoring of write operation progress and completion.
3Ease of operation
If write operations are suspended for read operations, then read access is enabled, but write throughput decreases and operational efficiency is reduced
Solution Approach 1:
The patent implements preliminary action by pre-allocating different latency periods and priority levels for read and write operations. Before conflicts occur, the system establishes a framework that allows both operation types to proceed concurrently with appropriate timing. This preliminary structuring enables write operations to continue without suspension while still allowing read access, maintaining write throughput while ensuring read availability.
Solution Approach 2:
The patent changes operational parameters by implementing variable latency periods and priority levels that can be adjusted based on operation type. By modifying these parameters dynamically, the system allows read and write operations to coexist without mutual suspension, optimizing both read accessibility and write throughput simultaneously through parameter-based operation management.
Data Source
AI summary
Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.