Variable Latency Request Arbitration Using Shift Register Scheduling

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Solution Overview

Problem

Merged processing pipelines that handle requests with different latencies face inefficiencies due to incorrect scheduling, leading to suboptimal processing of requests with varying completion cycles.

Innovation Solution

A technique involving a request arbiter that examines a shift register to determine available slots based on the number of cycles a request takes to complete, scheduling requests only when a matching slot is available, and shifting the register to manage requests across pipelines with different latencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If requests are scheduled without considering latency differences, then the processing pipeline can operate continuously, but processing efficiency deteriorates due to conflicts and suboptimal scheduling

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidrequest completion time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system performs preliminary scheduling of requests based on their latency requirements before execution. The scheduler examines the latency of each request and assigns it to an appropriate time slot in advance, ensuring that requests with different latencies are scheduled without conflicts. This preliminary planning prevents scheduling conflicts and optimizes processing efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The processing pipeline is segmented into multiple scheduling slots, each dedicated to handling requests with specific latency characteristics. By dividing the scheduling timeline into discrete segments and assigning requests to appropriate segments based on their latency requirements, the system avoids conflicts between requests with different completion times.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If a fixed scheduling approach is used, then the pipeline structure remains simple, but adaptability deteriorates when handling requests with varying latencies

Engineering Contradiction:
Improvehandling of variable latency requestsVSAvoidscheduling mechanism complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The scheduling mechanism dynamically adapts to the latency requirements of incoming requests. Instead of using a fixed scheduling pattern, the system adjusts the assignment of requests to time slots based on their individual latency characteristics. This dynamic approach allows the pipeline to efficiently handle variable latency requests while maintaining a relatively simple overall structure.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the scheduling parameters (time slot assignments) based on the latency parameter of each request. By varying the scheduling decisions according to the specific latency requirements of different requests, the system achieves high adaptability without requiring complex structural modifications to the pipeline.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10915359B2Variable latency request arbitration
Publication Date: 2021.02.09 ATI TECHNOLOGIES ULC
  • US10915359B2 patent drawing
  • US10915359B2 patent drawing
  • US10915359B2 patent drawing

AI summary

A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.