Variable-Length Bus Segmentation for Multi-Core Data Transfer
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Solution Overview
Problem
Conventional fixed length data buses in multi-core CPU arrays face limitations in data transfer capacity, throughput, and latency due to increased client count and physical length, leading to inefficiencies and resource waste, especially in complex algorithms with distant cores.
Innovation Solution
A variable length two-dimensional bus is introduced, dynamically subdivided into smaller segments with customizable paths using 4-way switches and meta tags to optimize data transfer, allowing flexible routing and minimizing control overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bus length is increased to connect more clients, then the client count increases, but the bus throughput degrades and latency increases
Solution Approach 1:
The patent divides the long bus into multiple segments by inserting buffer stations along the bus path. Each buffer station acts as an intermediate node that can buffer data and forward it to the next segment, effectively breaking the long bus into shorter functional segments while maintaining connectivity between all clients.
Solution Approach 2:
Buffer stations are introduced as intermediary components between clients on the bus. These buffer stations mediate data transfer by receiving data from one segment and forwarding it to the next, reducing the impact of bus length on throughput and enabling better control over data flow.
2Device complexity
If the bus is made serial to reduce complexity, then the device complexity decreases, but the transfer time increases
Solution Approach 1:
The patent segments the serial bus into multiple parallel sub-buses by introducing buffer stations with multiple output ports. This allows data to be transmitted over multiple parallel paths simultaneously, reducing transfer time while maintaining the simplicity of individual serial connections.
Solution Approach 2:
The patent transitions from a single-dimensional serial bus to a multi-dimensional parallel bus structure by adding buffer stations with multiple outputs. This dimensional expansion allows simultaneous data transmission across multiple paths, reducing transfer time without significantly increasing complexity.
3Productivity
If the bus is made parallel to increase throughput, then the bus bandwidth increases, but the layout and synchronization requirements become more complex
Solution Approach 1:
The patent creates parallel paths by segmenting the bus through buffer stations with multiple outputs. Each parallel path remains relatively simple and can be managed independently, reducing the overall layout and synchronization complexity compared to a monolithic parallel bus.
Solution Approach 2:
Buffer stations serve as intermediaries that simplify parallel bus management by providing controlled data forwarding between paths. These intermediaries handle the synchronization and routing decisions, reducing the complexity of direct parallel connections between all clients.
4Ease of operation
If cach transfer occupies the whole bus, then the data transfer is simple, but the bus resources are wasted for long transfers
Solution Approach 1:
The patent segments the bus so that cach transfers only occupy the relevant segment rather than the entire bus. Buffer stations act as boundaries that limit the scope of cach transfers, allowing other segments to utilize bus resources simultaneously and reducing overall resource waste.
Solution Approach 2:
The patent implements local quality by making each bus segment independently controllable through buffer stations. This allows cach transfers to be localized to specific segments, optimizing resource utilization in each local area without affecting the entire bus system.
Data Source
AI summary
A variable length bus that is flexible to increase the number of short hanl transfers without severely impeding the total bus capability, thus increasing total bus throughput and decreasing average latency. The variable length bus also makes the distribution of the bus manageable using very simple RAPC cores, minimizing control overhead.