Variable Length Instruction Encoding via Alias Addressing

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Solution Overview

Problem

Legacy processors face inefficiencies in mode switching between different instruction lengths, requiring manual mode bit setting, leading to overhead in code size, cycles, and performance impacts due to frequent mode changes, especially when reusing legacy code modules.

Innovation Solution

Implementing automatic mode switching between alias address spaces, allowing the processor to dynamically switch between different instruction lengths without manual intervention by using a program sequencer to generate instruction addresses and an execution unit to execute instructions in either mode, utilizing a common memory space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If manual mode bit setting is used to switch between different instruction lengths, then mode switching capability is achieved, but code size increases and execution cycles increase

Engineering Contradiction:

Improvemode switching capabilityVSAvoidcode size

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The processor automatically detects the address space of the current instruction and switches modes accordingly, eliminating the need for manual mode bit setting. The system serves itself by using the instruction address to determine the appropriate mode, thereby removing the overhead of mode change instructions from the code.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The invention changes the parameter used for mode selection from a manually set mode bit to the instruction address space. By monitoring which address space (first or second) the instruction belongs to, the processor automatically selects the appropriate mode, eliminating the need for separate mode change instructions and reducing code size.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If manual mode bit setting is used to switch between different instruction lengths, then mode switching capability is achieved, but execution time increases

Engineering Contradiction:

Improvemode switching capabilityVSAvoidexecution cycles

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The mode is determined in advance by the address space of the instruction before execution begins. The processor is pre-configured to associate the first address space with the first mode and the second address space with the second mode, so no time is spent on mode switching during execution.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If mode bit is set to switch between legacy mode and new mode, then new instruction types can be executed, but legacy code modules must be modified

Engineering Contradiction:

Improveinstruction type compatibilityVSAvoidcode module reusability

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The code is segmented into different address spaces: legacy code modules remain in the first address space and new instruction types are placed in the second address space. This segmentation allows legacy code to be reused without modification while enabling new functionality in a separate namespace.

Inventive Principle:

Principle #1Segmentation

4Adaptability or versatility

If mode switching is implemented using mode bit, then different instruction sets can be executed, but pipeline performance is impacted

Engineering Contradiction:

Improveinstruction set flexibilityVSAvoidpipeline performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8332621B2Implementation of variable length instruction encoding using alias addressing

Publication Date: 2012.12.11 ANALOG DEVICES INC

AI summary

A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.