Variable Length Private Key Generator Using Shift Register Permuter
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Solution Overview
Problem
Conventional cryptography systems are application-specific and rely on computationally intensive mathematical algorithms for generating secret keys of fixed lengths, limiting flexibility and efficiency in key generation.
Innovation Solution
A variable length private key generator using a permuter with shift registers, clocking modules, and an output module, which generates a key stream by permuting shift registers based on selected bits and clocking signals derived from primitive polynomials, allowing for dynamic key length generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional cryptography uses fixed-length secret keys generated by mathematical algorithms, then key generation is secure and standardized, but flexibility and adaptability to different key lengths are limited
Solution Approach 1:
The patent implements a dynamic key generation system where the length of the secret key is variable rather than fixed. The system uses a counter and feedback mechanism to generate keys of different lengths (e.g., 128-bit, 256-bit, 512-bit) from the same LFSR structure, allowing the key length to adapt to different cryptographic needs without requiring separate fixed-length generation systems for each key size.
Solution Approach 2:
The patent creates a universal key generation system where a single LFSR-based generator can produce multiple key lengths. The same hardware architecture and algorithm framework serve multiple functions by generating different key lengths through control of the counter and feedback mechanisms, eliminating the need for separate dedicated key generation systems for each key size requirement.
2Productivity
If conventional cryptography relies on computationally intensive mathematical algorithms for key generation, then key security is maintained, but system resource consumption and generation speed are reduced
Solution Approach 1:
The patent replaces complex mathematical algorithms with a linear feedback shift register (LFSR) mechanism that operates more efficiently. Instead of relying on intensive mathematical computations, the system uses bitwise operations and feedback loops within the LFSR to generate pseudo-random key streams, significantly reducing computational resource consumption and increasing key generation speed while maintaining cryptographic security.
Solution Approach 2:
The patent changes the operational parameters from mathematical algorithm complexity to LFSR state transitions. By controlling the counter values and feedback connections within the LFSR, the system generates keys through parameter manipulation of the register states rather than through computationally intensive mathematical operations, thereby improving productivity and reducing energy consumption.
3Adaptability or versatility
If conventional cryptography uses application-specific key generation, then key generation is optimized for specific applications, but versatility across different applications is limited
Solution Approach 1:
The patent develops a universal key generation system that can serve multiple applications through a single LFSR-based architecture. The system generates keys of variable lengths suitable for different cryptographic applications (e.g., stream ciphers, block ciphers, key derivation) using the same fundamental mechanism, making it easier to implement across diverse applications compared to maintaining separate application-specific key generation systems.
Data Source
AI summary
The present invention relates to a variable length private key generator. According to one embodiment, the variable length private key generator includes a permuter. The permuter is configured to generate a key stream of a desired length by permuting a plurality of shift registers. The permuter includes the plurality of shift registers, a plurality of clocking modules, and/or an output module. Each clocking module corresponds to a different one of the plurality of shift registers and is configured to generate a clocking signal based on selected bits of the corresponding shift register. The output module is configured to output the key stream based on at least one clocking signal and output of at least one of the plurality of shift registers.