Variable-Length Stream Decoding with Bit Spill-Over Alignment

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Solution Overview

Problem

Variable length encoded data streams present challenges in parallel decoding operations due to lack of byte alignment markers, leading to sequential processing that limits throughput and speed.

Innovation Solution

A decoder architecture that includes alignment logic to compensate for bit spill-over, allowing input lines to be aligned at symbol boundaries, enabling parallel processing through tokenizer and output generator logic to generate decoded data words.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential processing is used to decode variable length encoded data streams, then decoding accuracy is maintained, but throughput and speed are limited

Engineering Contradiction:
ImprovethroughputVSAvoiddecoder architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The decoder architecture is segmented into multiple independent processing units (tokenizer, alignment logic, output generator) that can operate in parallel. Each unit handles a specific aspect of the decoding process, allowing simultaneous processing of multiple data elements while maintaining overall decoding accuracy through coordinated operation of the segmented components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The alignment logic performs preliminary action by pre-aligning input data to symbol boundaries before the main decoding process. This preliminary alignment compensates for bit spill-over from previous lines, ensuring that parallel processing units receive properly synchronized input data, which enables accurate parallel decoding without requiring sequential processing.

Inventive Principle:
Principle #10Preliminary action

2Speed

If parallel processing is implemented to increase throughput, then decoding speed improves, but handling variable length symbols becomes complex due to lack of byte alignment markers

Engineering Contradiction:
Improvedecoding speedVSAvoidalignment logic complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The alignment logic acts as an intermediary component between the input data stream and the parallel processing units. It mediates the variable length symbol streams by detecting and compensating for bit spill-over, realigning data to symbol boundaries, and providing synchronized input to multiple processing units. This intermediary function enables parallel processing while managing the complexity of variable length encoding.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The alignment logic dynamically changes the parameter of data alignment by adjusting the starting position of input lines based on detected bit spill-over. This parameter adjustment compensates for variable length symbol variations, allowing parallel processing units to operate with properly aligned data without requiring complex synchronization mechanisms.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If serialized processing is used, then simplicity is maintained, but high bandwidth decompression cannot be achieved

Engineering Contradiction:
ImprovebandwidthVSAvoidprocessing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The parallel decoder architecture enables continuous useful action by maintaining multiple processing units that operate simultaneously throughout the decoding process. Unlike sequential processing where other units remain idle, all processing units continuously work on different aspects of the data stream, maximizing bandwidth utilization and eliminating idle time while maintaining high throughput.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8824569B2High bandwidth decompression of variable length encoded data streams
Publication Date: 2014.09.02 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8824569B2 patent drawing
  • US8824569B2 patent drawing
  • US8824569B2 patent drawing

AI summary

Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.