Variable Memory Page Architecture for Parallel Section Access
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Solution Overview
Problem
Existing memory devices face inefficiencies due to fixed page sizes that lead to unnecessary energy consumption and die space usage when accessing unused memory cells, particularly in volatile and non-volatile memory architectures.
Innovation Solution
A variable page size architecture that dynamically changes the size of memory pages by accessing multiple rows in parallel, utilizing multiple memory sections with their own sense components, allowing for flexible and efficient access of subsets of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large memory page size is used, then performance is improved through parallel access, but power consumption increases due to accessing unused memory cells
Solution Approach 1:
The memory array is divided into multiple independently accessible memory sections, each with its own sense components. This segmentation allows the system to access only the specific section containing the desired data, rather than activating entire large pages, thereby reducing power consumption while maintaining performance through selective parallel access.
Solution Approach 2:
The page size is made dynamically adjustable rather than fixed. The system can adaptively select the appropriate page size based on the actual data access requirements, enabling optimal performance when large pages are needed while conserving power when smaller access patterns suffice.
2Productivity
If a large memory page size is used, then performance is improved, but die space increases due to unnecessary components
Solution Approach 1:
By segmenting the memory array into multiple smaller sections, each section requires its own sense components only for that section. This eliminates the need for sense components covering the entire large page area, reducing die space while preserving the ability to achieve high performance through parallel access across multiple sections.
Solution Approach 2:
Each memory section is designed to be independently functional with its own sense components, allowing any section to serve as the active page. This universal design enables the system to achieve large effective page sizes through parallel access to multiple sections without requiring sense components for all possible cells simultaneously.
3Device complexity
If fixed page size architecture is used, then device complexity is reduced, but adaptability to different access patterns is limited
Solution Approach 1:
The memory system implements dynamic page size adjustment capability, allowing the page size to be modified based on access patterns. This maintains relatively simple device architecture while providing adaptability to different access requirements, resolving the contradiction between complexity and versatility.
Solution Approach 2:
The system enables changing the page size parameter dynamically without requiring fundamental architectural changes. This allows adaptation to different access patterns while maintaining the underlying simple memory structure, achieving versatility with minimal increase in device complexity.
Data Source
AI summary
Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.