Variable Memory Page Sizing for Lower-Power Cell Access
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Solution Overview
Problem
Static memory page sizes limit the flexibility and potential improvements in memory devices, such as increased memory cell density, read/write speeds, reliability, data retention, and reduced power consumption.
Innovation Solution
Implementing a variable page size system that allows memory cells to be accessed in tailored subsets or supersets, dynamically adjusting the page size based on specific use or application, thereby optimizing resource usage and access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If static memory page sizes are used, then memory device structure is simple, but flexibility and performance improvement are limited
Solution Approach 1:
The patent implements variable page sizes that can be dynamically changed during operation. The memory device transitions from static page size configurations to dynamic page size adjustment, allowing the system to optimize performance for different workloads by changing page sizes on-the-fly without requiring complex structural modifications to the memory array itself.
Solution Approach 2:
The patent changes the parameter of page size from fixed to variable. By implementing multiple page size options (e.g., 512 bytes, 1 KB, 2 KB, 4 KB) and allowing dynamic selection among them, the system achieves greater flexibility while maintaining relatively simple memory device structure through software-controlled parameter adjustment rather than hardware complexity.
2Productivity
If larger memory page sizes are used, then more memory cells can be accessed, but power consumption increases
Solution Approach 1:
The patent enables dynamic adjustment of page size based on actual access requirements. Instead of always activating large pages that consume more power, the system can switch to smaller page sizes when only a portion of memory cells needs to be accessed, thereby reducing power consumption while maintaining the capability to access larger memory capacities when needed.
Solution Approach 2:
The patent allows activation of only the necessary portion of memory cells rather than always activating entire large pages. By implementing variable page sizes, the system can activate partial sets of memory cells corresponding to the actual data access needs, avoiding the excessive power consumption associated with activating entire large pages when only small portions are required.
3Productivity
If variable page sizes are implemented, then resource efficiency improves, but control complexity increases
Solution Approach 1:
The patent implements a universal page size control mechanism that handles multiple page size configurations through a unified interface. The memory device can operate with different page sizes (512 bytes, 1 KB, 2 KB, 4 KB) using the same control logic and command structure, avoiding the need for separate control paths for each page size and thereby limiting the increase in control complexity.
4Productivity
If static page sizes are used, then manufacturing is simpler, but performance optimization is limited
Solution Approach 1:
The patent achieves performance optimization through parameter changes (page size selection) rather than through complex manufacturing variations. By implementing variable page sizes through software control and logical addressing rather than requiring different physical memory structures, the system maintains ease of manufacture while enabling performance optimization for different application scenarios.
Data Source
AI summary
Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.