Variable Nanosheet GAA Layout for Lower Power Logic Cells
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Solution Overview
Problem
Conventional Gate-All-Around (GAA) devices have a fixed number of nanosheets, limiting their ability to achieve lowest power consumption due to a fundamental constraint on the number of nanosheets per device, which restricts power and performance optimization.
Innovation Solution
The proposed solution involves creating additional logic areas on the same GAA wafer with a reduced number of nanosheets, allowing for flexible design options by using extra masks and minimal additional processing steps, enabling the creation of devices with varying nanosheet counts, such as N and N−M, to reduce cell-level capacitance and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a fixed number of nanosheets is used in conventional GAA devices, then the device structure is simple and fabrication is straightforward, but power consumption cannot be optimized to the lowest level due to the fundamental limitation on nanosheet count
Solution Approach 1:
The patent divides the GAA device into multiple logic areas (first logic area, second logic area, etc.) on the same wafer, where each area can have a different number of nanosheets (N, N-M1, N-M2, etc.). This segmentation allows different devices within the same wafer to have customized nanosheet counts optimized for their specific power and performance requirements, resolving the contradiction between fixed structure and design flexibility.
Solution Approach 2:
The patent implements local quality by allowing different regions of the wafer to have different nanosheet configurations. Specifically, the first logic area has N nanosheets, the second logic area has N-M1 nanosheets, and the third logic area has N-M2 nanosheets. This enables each local area to be optimized independently for its specific application, achieving both low power consumption and design flexibility simultaneously.
2Adaptability or versatility
If additional processing steps and masks are used to create variable nanosheet counts, then design flexibility and power optimization are improved, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent applies preliminary action by forming all nanosheets (including those that will be partially removed) in a single initial stacking process before any selective removal. The nanosheet stack is prepared once with N nanosheets, and then selective removal is performed in subsequent steps. This preliminary formation simplifies the overall process compared to forming different numbers of nanosheets in each area from scratch.
Solution Approach 2:
The patent uses the discarding principle by selectively removing M1 nanosheets from the second logic area and M2 nanosheets from the third logic area after the initial stack formation. The removed nanosheets are discarded, while the remaining nanosheets are recovered and used for the final device structure. This approach allows variable nanosheet counts to be achieved through simple removal processes rather than complex selective formation processes.
Data Source
AI summary
Disclosed are gate-all-around (GAA) devices formed on a nanosheet wafer that includes multiple nanosheet (NS) structures including first and second NS structures. The first NS structure may include N nanosheets, where N≥2. All N nanosheets may function as channels in the first NS structure. The second NS structure may include one or more nanosheets in which N−M of them function as channels, where 1≤M<N.