Variable-Offset LDO for Stable SAR ADC Reference Voltage

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Solution Overview

Problem

Existing ADC circuits face distortion issues due to changes in reference voltage caused by peak current, leading to inaccurate digital signal generation.

Innovation Solution

The proposed solution involves using a low dropout (LDO) regulator with a variable offset and a sub-ranging successive approximation register (SAR) ADC, which employs alternating reference voltage generators and decoupling capacitors to stabilize the reference voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a reference voltage generator with high output current is used to prevent distortion, then the reference voltage stability is improved, but the power consumption and device complexity increase

Engineering Contradiction:
Improvereference voltage stabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The reference voltage generator is divided into multiple segments: a main reference voltage generator, a peak current generator, and a capacitor. The peak current generator operates only during specific time periods when high current is needed, while the capacitor maintains voltage stability during other periods. This segmentation allows the system to achieve high reference voltage stability without continuously operating high-current components, thereby reducing overall device complexity and power consumption.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a reference voltage capacitor with high capacity is used to maintain stable reference voltage, then the reference voltage stability is improved, but the area occupied by the capacitor increases

Engineering Contradiction:
Improvereference voltage stabilityVSAvoidcapacitor area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The system employs periodic action by controlling the peak current generator to operate only during specific time periods (e.g., during sampling phases) rather than continuously. The capacitor is charged during these periodic high-current periods and then maintains the reference voltage during intermediate periods. This periodic operation allows the use of a smaller capacitor compared to continuous operation, significantly reducing the area occupied by the capacitor while maintaining reference voltage stability.

Inventive Principle:
Principle #19Periodic action

3Productivity

If peak current is supplied to the ADC for high-frequency switching operation, then the ADC performance is improved, but the reference voltage changes causing distortion

Engineering Contradiction:
ImproveADC conversion speedVSAvoidreference voltage stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The capacitor serves as an intermediary energy storage element between the peak current generator and the ADC. During high-frequency switching operations, the capacitor supplies the required peak current to the ADC, acting as a buffer that isolates the reference voltage generator from direct current demands. This intermediary approach allows the ADC to operate at high speeds while the reference voltage generator maintains stable output, preventing distortion caused by direct coupling of peak current demands.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces distortion by maintaining a stable reference voltage, allowing for accurate analog-to-digital conversion without the need for large capacitors or high output current generators.

Implementation Method 1

an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12321185B2Low dropout regulator providing variable offset and analog to digital conversion circuit including the same
Publication Date: 2025.06.03 SAMSUNG ELECTRONICS CO LTD
  • US12321185B2 patent drawing
  • US12321185B2 patent drawing
  • US12321185B2 patent drawing

AI summary

A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.