Variable Padding Packets for Link Clock Deviation Compensation

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Solution Overview

Problem

Clock frequency deviation between two ends of a link in high-speed serial bus communication can cause data loss or buffer underflow, leading to increased link bandwidth overhead due to the insertion of fixed-length padding packets.

Innovation Solution

A method that dynamically adjusts the length of padding packets based on the number of protocol-aware signal extenders in the link, generating a padding packet with a variable number of padding units to compensate for clock frequency deviation, thereby reducing bandwidth loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed-length padding packet is inserted to compensate for clock frequency deviation, then data loss and buffer underflow are prevented, but link bandwidth overhead increases

Engineering Contradiction:

Improvedata loss preventionVSAvoidlink bandwidth overhead

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies dynamics by making the padding packet length variable rather than fixed. The transmit end dynamically determines the padding packet length based on the detected clock frequency deviation magnitude, inserting shorter padding packets when deviation is small and longer padding packets when deviation is large, thus optimizing bandwidth utilization while maintaining reliable data transmission

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of padding packet length from a fixed value to a variable value that adapts to clock frequency deviation conditions. The system monitors clock deviation and adjusts the padding packet length parameter accordingly, transforming a static overhead structure into a dynamic one that responds to real-time synchronization needs

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a longer padding packet is used to ensure sufficient compensation for clock frequency deviation, then buffer underflow is prevented, but link bandwidth loss increases

Engineering Contradiction:

Improvebuffer underflow preventionVSAvoidlink bandwidth utilization

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by inserting only the necessary amount of padding required for clock frequency compensation. Instead of always using the maximum possible padding length, the system calculates and inserts just enough padding to prevent buffer underflow given the current clock deviation, avoiding excessive padding that would waste bandwidth

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent implements feedback mechanisms where the transmit end continuously monitors clock frequency deviation and uses this feedback information to adjust padding packet length. The receive end also provides feedback about buffer status, enabling the system to optimize padding insertion based on real-time synchronization conditions and bandwidth utilization needs

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250365125A1Method for compensating for clock frequency deviation between two ends of link, and communication port

Publication Date: 2025.11.27 HUAWEI TECH CO LTD

AI summary

This application discloses a method for compensating for a clock frequency deviation between two ends of a link, and a communication port. The method may be applied to a first port. The first port detects a quantity of protocol-aware signal extenders in a link between the first port and a second port, and generates a padding packet based on the quantity of protocol-aware signal extenders in the link. Then, the first port inserts the padding packet into a data stream to be sent to the second port.