Variable Page Table Structures for Granular Memory Allocation
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Solution Overview
Problem
Existing memory page systems have limited page size granularity, leading to inefficient memory allocation and excessive resource allocation to processes, as they often only support fixed page sizes like 4KB or 2MB, which does not accommodate intermediate memory requirements effectively.
Innovation Solution
Implementing variable page table structures with page table entries that indicate the size of memory pages, allowing for reduced memory utilization and improved granularity, and incorporating a page walk method that iteratively retrieves page tables of varying sizes based on the memory page size, along with prefetching adjacent tables to reduce retrieval frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed page sizes (4KB or 2MB) are used in memory allocation, then the memory system is simple to implement, but memory allocation efficiency deteriorates due to inability to accommodate intermediate memory requirements
Solution Approach 1:
The patent segments the page table structure into multiple levels (e.g., L1, L2, L3 page tables) where each level manages different ranges of virtual addresses. This segmentation allows the system to support variable page sizes by selectively allocating entries at different levels, thereby improving memory allocation efficiency without requiring a completely complex monolithic structure.
Solution Approach 2:
The patent implements dynamic page table structures where the number and size of page table entries can vary based on the actual memory allocation needs. Instead of fixed-size page tables, the system dynamically creates and manages page table levels, allowing intermediate page sizes (e.g., 64KB, 1MB) to be efficiently supported while maintaining implementation feasibility.
2Manufacturing precision
If variable page sizes are supported, then memory allocation granularity is improved, but the complexity of page table structures increases
Solution Approach 1:
The patent employs a nested page table structure where smaller page tables (e.g., L2 page tables) are contained within or referenced by larger page tables (e.g., L1 page tables). Each nested level manages a subset of the address space, allowing the system to achieve fine-grained memory allocation (supporting various page sizes from 4KB to 2MB) while organizing the complexity in a hierarchical, manageable manner.
Solution Approach 2:
The patent introduces an additional dimension to the page table structure by adding multiple levels of indirection. Instead of a single-dimensional flat page table, the system uses multi-level page tables where each level adds a dimension to the address translation process. This dimensional expansion enables support for variable page sizes and intermediate granularities without proportionally increasing the complexity of any single level.
3Reliability
If frequent page table retrieval is performed, then accurate memory translation is achieved, but system performance deteriorates due to retrieval overhead
Solution Approach 1:
The patent implements a prefetching mechanism that proactively loads page tables into the translation buffer before they are actually needed for address translation. By predicting which page tables will be needed based on current translation operations, the system prepares them in advance, reducing the frequency of slow retrieval operations and improving overall system performance while maintaining translation accuracy.
Solution Approach 2:
The patent introduces a translation buffer (TLB) as an intermediary cache between the page table structures and the address translation process. This intermediary holds recently used or frequently accessed page table entries, allowing the system to achieve accurate memory translation by first checking the fast buffer before performing full page table walks, thereby reducing retrieval overhead and improving system performance.
Data Source
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AI summary
Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables (114) dimensioned in a manner that optimizes memory usage by the data structures of the page system.