Variable Parity Encoder for Runtime-Reconfigurable BCH/RS Coding
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Solution Overview
Problem
Conventional BCH/RS encoders are not reconfigurable to change parameters at runtime, leading to inefficiencies in modern applications like solid-state disk flash controllers, where reconfiguration time is critical and non-constant multipliers increase the encoder's area, making them less efficient.
Innovation Solution
A variable parity encoder design that generates intermediate and parity bits using minimal polynomials, allowing for on-the-fly reconfiguration of the maximum error limit in less than three clock cycles, implemented using a combination of division and multiplication circuits with shared Galois Field multipliers, reducing the encoder's silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-constant GF multipliers are implemented to support reconfigurable BCH/RS encoders, then the encoder can change parameters at runtime, but the area of the encoder significantly increases
Solution Approach 1:
The encoder is divided into two functional paths: a first path for generating intermediate bits using division by minimal polynomials, and a second path for generating parity bits using multiplication by the same minimal polynomials. This segmentation allows each path to use optimized circuitry (division for configuration, multiplication for parity generation) rather than requiring full reconfigurable multiplication capability throughout the entire encoder, thereby reducing overall area while maintaining reconfigurability.
Solution Approach 2:
The same set of minimal polynomials is used for both division operations (in the first path for generating intermediate bits) and multiplication operations (in the second path for generating parity bits). This multi-functionality allows a single set of polynomial coefficients to serve dual purposes, eliminating the need for separate reconfigurable multiplier circuits and reducing the encoder area while preserving the ability to change parameters at runtime.
2Adaptability or versatility
If a wrapper approach is used around a non-reconfigurable encoder, then reconfigurability is achieved, but the area becomes approximately twice as large as non-reconfigurable designs
Solution Approach 1:
The division circuit and multiplication circuit are merged into a unified structure where the same minimal polynomial coefficients are shared between both operations. Instead of having separate wrapper circuits around a non-reconfigurable encoder, the invention integrates the reconfiguration capability directly into the core encoding process through shared polynomial resources, reducing the area overhead from approximately 2x to a much smaller increment.
3Adaptability or versatility
If reconfiguration is implemented to change maximum error limit at runtime, then adaptability improves, but the coefficients of LFSR become non-constant requiring non-constant GF multipliers
Solution Approach 1:
The encoder implements dynamic reconfiguration by allowing the selection of different minimal polynomials based on the desired maximum error limit T. The first path dynamically performs division by the appropriate minimal polynomial to generate intermediate bits, and the second path dynamically multiplies by the same minimal polynomial to generate parity bits. This dynamic approach allows runtime reconfiguration while maintaining constant coefficients for each selected polynomial, avoiding the need for fully non-constant multipliers.
Data Source
AI summary
An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.