Semiconductor Gate Formation with Variable Pitch Spacers
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Solution Overview
Problem
Conventional semiconductor processes face challenges in forming gates with different pitches and dimensions, particularly due to inferior performance of poly-silicon gates caused by boron penetration and depletion effects, which affect the quality and efficiency of multi-gate MOSFET devices as they scale down in size.
Innovation Solution
A semiconductor process using sidewall image transfer (SIT) techniques forms gates with different pitches and dimensions by creating mandrels and spacers with varying pitches and thicknesses, allowing for the transfer of spacer layouts to the gate layer, enabling the formation of gates with unique geometries and dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional poly-silicon gates are used, then manufacturing compatibility is maintained, but performance deteriorates due to boron penetration and depletion effects
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional poly-silicon to work function metals (such as tungsten, molybdenum, or titanium nitride). This material substitution eliminates boron penetration and depletion effects while maintaining compatibility with existing manufacturing processes, thereby resolving the contradiction between manufacturing compatibility and gate performance
Solution Approach 2:
The patent employs composite gate structures combining work function metals with high-k dielectric materials. This composite approach provides both the electrical performance benefits of work function metals (eliminating boron-related issues) and the capacitance advantages of high-k materials, while remaining compatible with standard fabrication processes
2Area of moving object
If gate size is reduced for miniaturization, then device density increases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent uses preliminary patterning steps including mandrel formation and spacer deposition before final gate definition. These preliminary actions establish precise geometric templates that guide subsequent etching processes, enabling accurate gate dimension control even at reduced gate sizes and maintaining manufacturing precision during miniaturization
Solution Approach 2:
The patent transitions from two-dimensional planar gating to three-dimensional multi-gate structures (such as FinFET or nanosheet configurations). This dimensional change increases the effective gate area and channel control without proportionally increasing the planar footprint, allowing device density improvement while maintaining manufacturable gate dimensions through vertical scaling
Data Source
AI summary
A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.