Variable Pitch Interconnect Lines Using Spacer Formation
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Solution Overview
Problem
Current semiconductor fabrication techniques, such as Self-Aligned Quadruple Patterning (SAQP), struggle to achieve variable pitch and line widths in Back-End-Of-Line (BEOL) interconnect systems, especially at pitches below 38 nm, due to lithographic variability, which can lead to time-delayed shorting and dielectric breakdown.
Innovation Solution
The method involves forming semiconductor cells with metal lines separated by spacers made of dielectric isolation material, where the line widths and spacer widths are accurately controlled to provide electrical isolation, allowing for variable line widths and pitches, including those as low as 36 nm or less, by using a process that includes patterning mandrels and forming mandrel spacers to create the metal lines and spacers within a dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional lithographic techniques (SAQP) are used to form interconnection lines, then patterning resolution can be extended beyond 80 nm pitch, but the minimum pitch is limited to about 20 nm and variable pitch/line widths are difficult to achieve
Solution Approach 1:
The pitch control is segmented into two independent components: (1) mandrel pitch controlled by lithography, and (2) spacer width controlled by deposition thickness. This segmentation allows the final line pitch to be adjusted by varying spacer deposition without requiring re-lithography, enabling variable pitch while maintaining lithographic resolution benefits.
Solution Approach 2:
The invention transitions from two-dimensional lithographic patterning to three-dimensional spacer formation. By depositing conformal spacer layers around mandrels and then anisotropically etching, the pitch control is moved to the vertical deposition dimension rather than the lateral lithographic dimension, enabling pitch adjustment without compromising lithographic resolution.
2Length of moving object
If spaces between metal lines become too narrow due to lithographic variability, then pitch can be reduced, but time delayed shorting and dielectric breakdown occur
Solution Approach 1:
The invention replaces lithographic mechanical patterning with a deposition-based spacer formation process. The spacer width is determined by conformal deposition thickness rather than lithographic feature size, eliminating the direct link between lithographic variability and spacer dimension control. This substitution ensures reliable electrical isolation even at small pitches.
Solution Approach 2:
The spacer formation process is self-aligning and self-regulating. The conformal deposition automatically ensures uniform spacer width around each mandrel, and the subsequent anisotropic etch self-stop at the mandrel surface ensures consistent spacing. This self-service mechanism eliminates the need for additional alignment steps and ensures reliable pitch control.
3Adaptability or versatility
If variable line widths are required for different functions (power vs signal lines), then interconnect flexibility is improved, but conventional SAQP processes cannot achieve this variability
Solution Approach 1:
The mandrels are formed first with uniform dimensions using conventional lithography. Then, spacer deposition is performed to create the final pitch structure. This preliminary action separates the lithographic patterning step from the pitch definition step, allowing pitch and line width variation to be introduced in subsequent deposition steps without complicating the lithographic process.
Solution Approach 2:
The invention enables local quality variation by allowing different spacer deposition thicknesses or selective spacer removal in different regions. This permits power lines to have larger pitch (wider spacing) while signal lines maintain minimum pitch, with each region optimized for its specific electrical requirements without requiring different lithographic processes.
4Manufacturing precision
If next generation lithographic techniques (EUV) are used to reduce lithographic variability, then pitch control may be improved, but development problems currently limit resolution to 40 nm pitch or less
Solution Approach 1:
The invention introduces spacers as an intermediary element between the lithographically-defined mandrels and the final metal interconnect lines. The spacers serve as the actual pitch-defining features, decoupling the final pitch control from lithographic capabilities. This intermediary approach allows pitch control to be determined by deposition processes rather than lithographic resolution limits.
Data Source
AI summary
A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines, the line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. An overall cell height of the cell is substantially equal to an integer multiple of a plurality of cell tracks, each cell track being a minimum pitch of the cell. The minimum pitch being defined by the minimum line width plus the minimum line spacer width. The minimum pitch is equal to or less than 36 nm. Not all of the line widths are substantially equal and every other line spacer width is substantially equal.