Variable-Length PLL Circuit for Fast Low-Power Phase Locking
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Solution Overview
Problem
Existing phase-locked loops in high bit-rate and low consumption transmission systems, such as IR-UWB technology, face challenges in optimizing energy efficiency due to their energy budget constraints, particularly in the design of phase-locked loops that affect the overall consumption.
Innovation Solution
A phase-locked loop circuit is designed with a circular shift register of variable length, controlled by multiple circuits and multiplexers, which adjusts the delay elements and voltage control to optimize the phase locking process, reducing energy consumption and improving locking speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional phase-locked loop is used in IR-UWB transmission systems, then the system can achieve phase locking functionality, but the energy consumption is too high given the tight energy budget constraints
Solution Approach 1:
The phase-locked loop is divided into two distinct operational modes: acquisition mode for fast initial phase locking and tracking mode for precise continuous phase following. This segmentation allows the system to use different circuit configurations optimized for each phase, reducing overall energy consumption while maintaining reliability.
Solution Approach 2:
The circuit dynamically switches between acquisition and tracking modes based on the locking state. The variable gain amplifier and delay line elements are actively controlled to provide different characteristics during acquisition versus tracking, optimizing performance and energy efficiency for each operational phase.
2Speed
If the phase-locked loop uses a fixed delay chain configuration, then the circuit structure is simple, but the locking speed is insufficient for high bit-rate transmission requirements
Solution Approach 1:
The delay line configuration is made dynamic through the use of multiplexers that can selectively connect different delay elements based on the operational mode. During acquisition mode, the delay line is configured to provide maximum delay for fine phase adjustment, while in tracking mode, the configuration is optimized for speed, allowing fast locking without excessive circuit complexity.
Solution Approach 2:
The same delay line elements serve multiple functions: they provide phase delay during acquisition mode and act as a tracking filter during tracking mode. This multi-functionality achieves fast locking capability without proportionally increasing circuit complexity, as the hardware is reused across different operational phases.
3Measurement precision
If the phase-locked loop uses high gain amplification, then the locking precision is improved, but the energy consumption increases significantly
Solution Approach 1:
The variable gain amplifier dynamically adjusts its gain based on the operational mode. During acquisition mode, high gain is applied to enhance phase detection precision for accurate locking. During tracking mode, the gain is reduced to lower power consumption while maintaining sufficient precision for continuous phase following, thus resolving the contradiction between precision and energy consumption.
Solution Approach 2:
The amplifier gain parameter is changed according to the operational phase. The system transitions from high gain during acquisition to lower gain during tracking, allowing the phase detection precision to be optimized when needed while minimizing energy consumption during the longer tracking period.
Data Source
Figure 1~3
Figure 2
Figure 4A~5A
AI summary
A Phase-locked loop circuit including: a local oscillator (14), configured to generate a timing signal (VLO); a variable- length shift register (19), controlled by the timing signal; and a feedback control circuit (2, 18, 20, 22, 24, 26), which receives a pulsed input signal (Vpis) and receives a local signal (Voce) from the shift register. The feedback control circuit detects whether each pulse of the input signal (Vpis) respects a condition of temporal proximity with a corresponding pulse of the local signal (Voce) and detects, for each pulse of the input signal (Vpis) that respects the proximity condition, whether the edge falls early, late, or within a predefined portion of the corresponding pulse of the local signal (Voce). The feedback control circuit controls the length of the shift register and the frequency of the timing signal (VLO), as a function of the detections made.