Variable Preamble Cycle for Memory Signal Collision Prevention
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Solution Overview
Problem
In high-speed memory systems, collisions occur between strobe signals and preamble signals generated by semiconductor memory devices due to unstable output data strobe signal generation and fixed cycle numbers, leading to timing mismatches during read operations.
Innovation Solution
A memory system and semiconductor memory device configuration that calculates a variable preamble cycle number by subtracting the burst length from the cycle number between dummy and read commands, allowing for dynamic generation of preamble signals to synchronize with the clock signal, preventing collisions between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed cycle number for preamble signal is used, then the implementation is simple, but collisions occur between strobe signals and preamble signals from multiple devices
Solution Approach 1:
The patent applies dynamics by making the preamble cycle number variable rather than fixed. Each semiconductor memory device dynamically adjusts its preamble cycle number based on the detected read command timing and calculated cycle values, allowing the system to adapt to different operational conditions and prevent signal collisions between multiple devices
Solution Approach 2:
The patent changes the parameter of preamble cycle number from a fixed value to a calculated variable. The memory device calculates the preamble cycle number by subtracting the burst length from the cycle number between dummy and read commands, thereby adjusting the timing parameters dynamically to avoid collisions while maintaining operational simplicity
2Speed
If the output data strobe signal frequency increases with clock signal, then the data transmission speed improves, but the initial signal generation becomes unstable
Solution Approach 1:
The patent applies preliminary action by generating the preamble signal before the main strobe signal. This preliminary signal preparation allows the output data strobe signal to stabilize its frequency and timing before actual data transmission begins, ensuring stable high-speed operation without compromising initial signal generation reliability
3Productivity
If multiple semiconductor memory devices share a common output data line, then the system integrates efficiently, but signal collisions occur during simultaneous read operations
Solution Approach 1:
The patent enables dynamic timing adjustment for each memory device on the common output data line. By calculating and applying device-specific preamble cycle numbers based on read command timing, each device can coordinate its signal output dynamically, preventing collisions while maintaining efficient system integration and utilization of the shared bus
Data Source
AI summary
An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.