3D Memory Strings with Variable Precharge Levels
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Solution Overview
Problem
The integration and operational reliability of two-dimensional nonvolatile memory devices have reached limits, necessitating the development of three-dimensional structures for improved performance, where memory cells are vertically stacked, and existing methods do not effectively address the differences in channel lengths and precharge levels during read operations.
Innovation Solution
A semiconductor device with memory strings of varying channel lengths, where bit lines are precharged to different levels based on channel length during read operations, allowing for adjusted precharge levels to compensate for differences in cell current and threshold voltage between long and short channel lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are vertically stacked in a three-dimensional structure to improve integration, then the degree of integration is improved, but the operational reliability deteriorates due to differences in channel lengths and precharge levels during read operations
Solution Approach 1:
The patent applies local quality by differentiating the precharge levels based on the specific channel length of memory strings. Memory strings with longer channel lengths receive higher precharge levels while shorter channel length strings receive lower precharge levels. This localized adjustment compensates for the inherent differences in electrical characteristics caused by the three-dimensional vertical stacking structure, thereby maintaining operational reliability while achieving high integration.
2Ease of manufacture
If memory strings with different channel lengths are used in the three-dimensional structure, then the manufacturing flexibility is improved, but the read operation complexity increases due to the need for different precharge levels
Solution Approach 1:
The patent segments the memory device into multiple read units, where each read unit is associated with specific memory strings having particular channel length characteristics. This segmentation allows the controller to manage different precharge levels in an organized manner, reducing the overall complexity by breaking down the control into manageable segments rather than handling all memory strings uniformly.
Solution Approach 2:
The patent implements preliminary action by precharging bit lines to appropriate levels before read operations begin. The controller determines the required precharge level based on the channel length characteristics of the target memory strings and applies the appropriate precharge level in advance. This preliminary preparation simplifies the subsequent read operation by eliminating the need for dynamic adjustments during the actual read process.
3Device complexity
If uniform precharge levels are applied to all memory strings, then the device complexity is reduced, but the measurement precision deteriorates due to inability to compensate for channel length differences
Solution Approach 1:
The patent applies parameter changes by varying the precharge level parameter according to the channel length of memory strings. Instead of using a fixed uniform precharge level, the system adjusts the precharge voltage parameter to match the electrical characteristics of each memory string group. This parameter adaptation improves the precision of read operations by ensuring that each memory string operates within its optimal voltage range, compensating for the effects of different channel lengths.
Data Source
AI summary
A semiconductor device includes a plurality of first memory strings each first memory string having a channel with a first length and a plurality of second memory strings each second memory string having a channel with a second length shorter than the first length. A method of operating the semiconductor device includes: performing a first read operation on the first read unit, wherein the first read unit includes the first memory cells sharing the same first word line among first memory cells included in the plurality of the first memory strings; and performing a second read operation on the second read unit, wherein the second read unit includes the second memory cells sharing the same second word line among second memory cells included in the plurality of the second memory strings.