Variable Precharge Pulse Width for Resistive Memory Read Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memories using resistance materials face reliability issues during read operations due to varying word line and bit line resistances, which affect the accuracy and efficiency of data retrieval.
Innovation Solution
The semiconductor memory design includes a memory cell array with a read circuit that precharges bit lines and applies read bias using varying pulse widths based on the resistance levels of memory cells, and a row selection circuit that adjusts pulse widths of row select signals according to the position of memory cells, ensuring consistent voltage levels and improved reliability during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed pulse width is used for precharging bit lines, then the read operation is simple to control, but the reading accuracy deteriorates due to varying bit line resistances
Solution Approach 1:
The patent applies dynamics by making the precharge pulse width variable rather than fixed. The read circuit dynamically adjusts the pulse width of the precharge signal based on the resistance characteristics of the selected bit line, allowing the system to adapt to different memory cell positions and achieve accurate reading despite varying resistances.
Solution Approach 2:
The patent changes the parameter of pulse width in the precharge signal. By varying this temporal parameter according to the selected bit line's resistance characteristics, the system optimizes the voltage level at the sense amplifier input, thereby improving reading accuracy without requiring fundamental changes to the read circuit architecture.
2Reliability
If memory cells are positioned at different locations in the array, then the memory capacity is maximized, but the reading reliability deteriorates due to varying word line and bit line resistances
Solution Approach 1:
The patent applies local quality by providing different precharge pulse widths tailored to specific bit lines or regions of the memory array. Instead of using a uniform approach, the system adjusts the precharge characteristics locally according to the resistance properties of each bit line, ensuring optimal reading conditions for memory cells at different positions within the array.
3Stability of the object's composition
If the precharge signal pulse width is increased, then the voltage level stability is improved, but the read operation time is extended
Solution Approach 1:
The system dynamically determines the appropriate precharge pulse width based on the selected bit line's resistance characteristics. This dynamic adjustment ensures that each bit line receives the optimal precharge duration needed to achieve stable voltage levels, avoiding both excessive precharge times and insufficient precharge, thereby optimizing the trade-off between stability and speed.
Data Source
AI summary
A semiconductor memory includes a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of bit lines, each bit line connected to a corresponding column of the memory cells; a column selection circuit configured to select at least one bit line in response to a column select signal; and a read circuit configured to precharge the selected bit line in response to a precharge signal, to apply a read bias to the precharged bit line in response to a read bias provision signal, and to read data from the memory cells. A resistance level of each of the memory cells varies according to data stored therein, and the read circuit reads data from a first memory cell of the plurality of memory cells in response to the precharge signal having a first pulse width and reads data from a second memory cell of the plurality of memory cells in response to the precharge signal having a second pulse width.