Variable Precision Floating-Point Rounding Circuit
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Solution Overview
Problem
The IEEE 754-2008 floating-point representation is prone to computational errors such as rounding, cancellation, and absorption errors due to its fixed bit length, leading to inaccuracies in computations, especially when dealing with large and small values.
Innovation Solution
A floating-point computation circuit with a load and store unit that converts floating-point values between internal and external memory formats, allowing for variable precision and supporting multiple formats like Custom Posit, Not Contiguous Posit, and Modified Posit, to minimize errors by dynamically adjusting precision based on computational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fixed-bit-length IEEE 754-2008 floating-point representation is used, then device complexity is reduced and ease of operation is improved, but manufacturing precision deteriorates due to rounding, cancellation, and absorption errors
Solution Approach 1:
The patent implements variable precision floating-point formats where the bit length of the fraction field dynamically adapts based on the exponent value. This allows the system to allocate more bits to the fraction when higher precision is needed (for small values with small exponents) and fewer bits when precision requirements are lower (for large values with large exponents), thereby improving computational precision while managing device complexity through conditional adaptation rather than fixed structure
Solution Approach 2:
The patent changes the parameter of fraction bit length from fixed to variable based on exponent thresholds. By defining different fraction lengths corresponding to different exponent ranges, the system optimizes precision for each magnitude range, reducing rounding errors for small numbers and absorption errors for large numbers, thus improving manufacturing precision without requiring a completely new computational architecture
2Manufacturing precision
If variable precision formats are implemented to reduce computational errors, then manufacturing precision is improved, but device complexity increases due to multiple format conversion circuits
Solution Approach 1:
The patent segments the exponent range into multiple intervals, each associated with a specific fraction bit length. By dividing the exponent space into discrete ranges (e.g., exponent ≤ -128 uses 64-bit fraction, -128 < exponent ≤ -64 uses 32-bit fraction, etc.), the system creates a structured approach to variable precision that simplifies the conversion logic compared to fully continuous variable precision, thereby managing device complexity while maintaining precision improvements
Solution Approach 2:
The patent introduces an intermediary mechanism in the load and store unit that automatically selects and applies the appropriate fraction bit length based on the exponent value. This intermediary layer handles the complexity of format conversion by encapsulating the selection logic, allowing the rest of the computational system to operate with simplified assumptions while still benefiting from variable precision where needed
3Manufacturing precision
If higher precision is used for all floating-point values, then manufacturing precision is improved, but loss of substance increases due to greater memory requirements
Solution Approach 1:
The patent applies local quality by assigning different precision levels to different regions of the floating-point value space based on their specific needs. Small floating-point values (with small exponents) receive higher precision (longer fraction fields) because they benefit more from reduced rounding errors, while large floating-point values (with large exponents) use lower precision since their primary error source is absorption rather than rounding. This localized precision allocation improves overall manufacturing precision while minimizing the increase in memory usage compared to uniform high precision
Data Source
AI summary
The present disclosure relates to a floating-point computation device comprising: a first floating-point (FP) operation circuit (3202) comprising a first processing unit (3204) configured to perform a first operation on at least one input FP value (F1, F2) to generate a result; a first rounder circuit (3206); and a first control circuit (3302) configured to control a bit or byte length applied by a rounding operation of the first rounder circuit (3206), wherein the control circuit (3302) is configured to apply a first bit or byte length (BLA) if the result of the first operation is to be stored to an internal memory of the floating-point computation device to be used for a subsequent operation, and to apply a second bit or byte length (BLS), different to the first bit or byte length, if the result of the first operation is to be stored to an external memory.