Variable Precision Floating-Point Adder Dual-Path Architecture
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) with fixed precision floating-point adders are inefficient in supporting a wide range of intermediate precisions, leading to limited functional density and increased area overhead when trying to implement variable precision floating-point arithmetic circuits.
Innovation Solution
A multi-precision floating-point adder with a dual-path architecture that splits input numbers into near and far paths based on exponent differences, incorporating subtraction, normalization, alignment, and addition/subtraction circuits, along with a multiplexer to selectively output results, and supporting various mantissa widths through right shifting, maximum shift lookup tables, and gating circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed precision floating-point adders are used in PLDs, then the circuit structure is simple and area is reduced, but the functional density is limited and intermediate precisions cannot be supported
Solution Approach 1:
The adder is divided into two separate paths: a near path for small exponent differences and a far path for large exponent differences. Each path is optimized for its specific precision requirements, allowing the circuit to support multiple intermediate precisions without requiring a completely new design for each precision level.
Solution Approach 2:
The circuit uses dynamic path selection based on the exponent difference between input operands. A selector circuit dynamically routes operations through the appropriate path (near or far) depending on the specific precision requirements, enabling adaptive support for various intermediate precisions including FP17, FP18, and FP20.
2Adaptability or versatility
If multiple precision floating-point adders are implemented, then functional density is improved, but area overhead increases significantly
Solution Approach 1:
The dual-path adder architecture serves multiple precision functions within a single unified circuit structure. The near path handles FP64 and intermediate precisions, while the far path handles FP32 and intermediate precisions, allowing one circuit to perform multiple precision operations that would traditionally require separate dedicated adders for each precision level.
Solution Approach 2:
The circuit changes its operational parameters (precision level, path selection, alignment amount) based on the input operands' characteristics. By dynamically adjusting the alignment amount and selecting different computational paths, the same physical circuit can efficiently support a wide range of precisions from FP32 to FP64 and all intermediate levels without requiring separate hardware for each precision.
3Measurement precision
If conventional floating-point adders are used, then the implementation is straightforward, but rounding accuracy for intermediate precisions deteriorates
Solution Approach 1:
The far path performs preliminary alignment of mantissas before addition by calculating the exact alignment amount based on exponent differences. This preliminary alignment ensures that intermediate precision operations maintain proper bit positioning and rounding accuracy before the actual addition occurs, preventing rounding errors that would occur with conventional approaches.
Solution Approach 2:
The alignment circuit acts as an intermediary between the input operands and the addition operation. It properly positions the mantissas at the correct alignment point before addition, ensuring that intermediate precision operations (FP17, FP18, FP20) maintain accurate rounding. The selector circuit serves as another intermediary that routes operations through the appropriate path based on precision requirements.
Data Source
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AI summary
An integrated circuit may include a floating- point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa values may be left justified, while the sticky bits are right justified. The hardware for the largest mantissa can be used to support the calculations for the smaller mantissas using no additional arithmetic structures, with only some multiplexing and decoding logic.