Variable Precision Floating-Point Computation Circuit
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Solution Overview
Problem
The IEEE 754-2008 standard's fixed-bit length representation of floating-point numbers leads to computational errors such as rounding, cancellation, and absorption errors, especially when dealing with large or very small numbers.
Innovation Solution
A floating-point computation circuit with an internal memory and a load and store unit that converts floating-point values between internal and external memory formats of varying precision, allowing for dynamic adjustment of precision based on the format type and identifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed-bit length floating-point representation (IEEE 754-2008) is used, then memory storage and processing are simplified, but computational errors such as rounding, cancellation, and absorption errors occur
Solution Approach 1:
The patent implements dynamic precision adjustment where the floating-point format can change based on operational requirements. The load and store unit dynamically converts between different precision formats (e.g., 32-bit, 64-bit, 128-bit) depending on whether the operation requires high precision or can use simplified representation, thus resolving the contradiction between simplicity and accuracy.
Solution Approach 2:
The patent changes the parameter of precision dynamically. By allowing the bit length and precision level to vary based on the specific computational needs, the system can achieve high accuracy when necessary while maintaining simplicity for routine operations, thereby resolving the contradiction between ease of processing and measurement precision.
2Measurement precision
If variable precision computing is implemented, then computational errors are reduced, but device complexity increases due to multiple format conversion circuits
Solution Approach 1:
The load and store unit is designed as a multi-functional component that handles multiple precision formats through a single integrated structure. Rather than having separate dedicated circuits for each format conversion, the universal unit can convert between various formats (32-bit, 64-bit, 128-bit) using a unified approach, thus reducing overall device complexity while maintaining high precision capabilities.
Solution Approach 2:
The patent introduces an intermediary conversion mechanism within the load and store unit that mediates between different precision formats. This intermediary structure simplifies the interaction between high-precision internal computations and standard-precision memory storage, reducing the complexity burden on the overall system while preserving computational accuracy.
3Measurement precision
If high precision floating-point formats are used for all operations, then computational accuracy is maximized, but memory footprint and processing time increase
Solution Approach 1:
The patent applies partial precision rather than excessive precision uniformly across all operations. The system uses high precision only when necessary (e.g., for intermediate calculations that require it) and employs simplified lower precision formats for operations where full precision is not needed, thus optimizing both accuracy and processing efficiency by avoiding unnecessary computational overhead.
Solution Approach 2:
The system dynamically adjusts the precision level based on the specific operation being performed. For critical calculations, high precision formats are activated; for routine operations, simplified formats are used. This dynamic adaptation ensures maximum accuracy when needed while maintaining high productivity through efficient use of computational resources.
Data Source
AI summary
The present disclosure relates to a floating-point computation circuit comprising: an internal memory (104, 114) storing one or more floating-point values in a first format; status registers (124) defining a plurality of floating-point number format types associated with corresponding identifiers, each format type indicating at least a maximum size (BIS, MBB); and a load and store unit (108, 118) for loading floating-point values from and storing floating-point values to an external memory (120, 122), the load and store unit (108, 118) being configured: to receive, in relation with a first store operation, a first floating-point value from the internal memory (104, 114) and a first of said identifiers; and to convert the first floating-point value from the first format to a first external memory format having a maximum size (BIS, MBB) defined by the floating-point number format type designated by the first identifier.