Variable Processing Period in Digital Logic Modules for Security
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Solution Overview
Problem
Current encryption/decryption processes in digital logic modules are vulnerable to analysis through current consumption patterns, making it difficult to protect sensitive information from intrusive attacks.
Innovation Solution
Introducing a system that randomly or pseudo-randomly alters the number of clock cycles required to complete an algorithm, thereby reshaping current consumption patterns to obscure analysis, using additional combinatorial circuits to vary the processing time periods in digital logic modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed processing time period is used for encryption/decryption algorithms, then the processing is efficient and predictable, but the current consumption pattern becomes vulnerable to analysis
Solution Approach 1:
The patent applies dynamics by making the processing time period variable rather than fixed. The controller dynamically adjusts the number of clock cycles based on random or pseudo-random numbers, causing the processing time to fluctuate between different iterations. This dynamic variation obscures the current consumption pattern, making it difficult for attackers to predict or analyze the encryption/decryption process, thereby resolving the contradiction between security reliability and device complexity.
Solution Approach 2:
The patent changes the parameter of processing time from a fixed value to a variable value. By introducing random or pseudo-random number generation, the number of clock cycles required for encryption/decryption is changed dynamically. This parameter change transforms the predictable current consumption pattern into an unpredictable one, enhancing security while introducing controlled complexity through the randomization mechanism.
2Reliability
If the processing time is varied randomly to obscure current consumption patterns, then security analysis becomes more difficult, but the processing efficiency decreases
Solution Approach 1:
The patent applies partial action by performing encryption/decryption operations with varying degrees of completeness based on random selection. Instead of always executing the full algorithm, the system may terminate early or extend beyond the standard processing time according to randomly generated numbers. This partial/excessive action approach obscures processing patterns effectively while limiting the impact on average processing efficiency, as the variation is controlled rather than completely random.
3Reliability
If additional combinatorial circuits are added to vary processing time, then current analysis resistance improves, but the device complexity increases
Solution Approach 1:
The patent applies universality by designing the controller to serve multiple functions: it controls the normal encryption/decryption process, generates random or pseudo-random numbers, determines processing time variation, and manages the combinatorial circuit activation. This multi-functional approach reduces the need for separate dedicated circuits for each function, thereby enhancing security through increased circuit complexity while minimizing the overall device complexity through functional integration.
Data Source
AI summary
The invention is a system for modifying the processing period in a digital logic module. The invention comprises the following. A processing circuit is configured to receive an input in order to create an output. A controller is coupled to the processing circuit and is configured to track L manipulations, wherein L is an integer. The controller is further configured to send a select signal to the processing circuit and to cause the processing circuit to manipulate the input over N clock cycles. N is an integer and N is less than or equal to L. N varies over the plurality of processing time periods. An output port is coupled to the processing circuit and is configured to convey the output.