Variable-Resolution Sigma-Delta DAC Dithering for Idle Tones
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Solution Overview
Problem
Sigma-Delta digital-to-analog converters (DACs) produce unwanted idle tones due to the quantization process, which limit the spurious free dynamic range (SFDR) and signal-to-noise-and-distortion (SINAD) by introducing undesired high tones in the analog output.
Innovation Solution
The implementation of a Sigma-Delta modulator with a random or pseudo-random sequence generator that introduces a dithering error signal, de-correlating the idle tones and attenuating them by adding a non-correlated, high-frequency signal with zero average, which is filtered by the modulator loop, thereby reducing the idle tones without additional filtering at the analog output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a Sigma-Delta modulator uses a fixed resolution quantizer, then the device complexity is low and ease of manufacture is high, but idle tones are produced that limit SFDR and SINAD
Solution Approach 1:
The patent applies dynamics by making the quantizer resolution variable rather than fixed. The modulator switches between different quantizer resolutions (e.g., 1-bit, 2-bit, 3-bit) based on a pseudo-random sequence, which dynamically changes the quantization behavior to eliminate idle tones while maintaining simplicity in each individual quantizer design
Solution Approach 2:
The patent changes the resolution parameter of the quantizer dynamically using a pseudo-random sequence. By varying the quantizer resolution parameter according to the pseudo-random sequence, the system eliminates the periodicity that causes idle tones, thereby improving SFDR and SINAD without requiring complex additional filtering circuitry
2Manufacturing precision
If dithering is implemented using a pseudo-random sequence to remove idle tones, then SFDR and SINAD improve, but the device complexity increases due to additional circuitry
Solution Approach 1:
The patent extracts the dithering function from external filtering circuitry and integrates it directly into the digital domain within the modulator. By implementing the pseudo-random sequence generation and application inside the digital modulator, the system removes idle tones without requiring additional analog filtering components, thereby reducing overall device complexity
Solution Approach 2:
The patent uses a pseudo-random sequence as an intermediary element that mediates between the quantizer and the output. This pseudo-random sequence is generated digitally and applied to the quantizer input to randomize the quantization error, effectively eliminating idle tones through digital processing rather than analog filtering
Data Source
AI summary
A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M−N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.