Variable-Resolution Sigma-Delta Quantizer for Idle Tone Suppression
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Solution Overview
Problem
Sigma-delta analog-to-digital converters (ADCs) produce unwanted idle tones due to the quantization process, which limit the spurious free dynamic range and signal-to-noise-and-distortion (SINAD) of devices, especially when encountering direct current (DC) inputs that are rational fractions of the quantization step.
Innovation Solution
A multi-bit sigma-delta ADC with a variable resolution quantizer that introduces a pseudo-random or random dithering signal, allowing the quantization error to be noise-shaped and filtered within the modulator loop, eliminating the need for additional output filters and maintaining stability even with large input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-bit sigma-delta ADC uses a fixed resolution quantizer, then the device structure is simple, but idle tones appear in the output limiting SINAD
Solution Approach 1:
The quantizer resolution is made dynamic by varying the number of output levels according to a pseudo-random sequence. The quantizer switches between different resolution states (e.g., 3-level, 5-level, 7-level) based on the dithering sequence, which breaks the periodicity of idle tones and improves SINAD without requiring complex additional filtering circuitry.
Solution Approach 2:
The quantization parameter (number of output levels) is changed dynamically according to a pseudo-random sequence. By varying the resolution parameter N(n) between different values, the quantization error becomes unpredictable, which eliminates the coherent idle tones that limit SINAD in fixed-resolution quantizers.
2Reliability
If dithering is added to remove idle tones, then SINAD improves, but additional filtering circuitry is required
Solution Approach 1:
The sigma-delta modulator loop itself performs the filtering function. The noise-shaping capability of the feedback loop automatically filters the quantization error, eliminating the need for separate output filtering circuitry. The system uses its own inherent structure to achieve both dithering and filtering functions.
Solution Approach 2:
The dithering function is merged with the quantizer structure, and the filtering function is merged with the feedback loop. By combining these functions into the existing modulator architecture, no additional filtering circuitry is required beyond what is already present in the sigma-delta ADC.
3Reliability
If quantizer resolution is varied to dither the signal, then idle tones are removed, but the number of comparators increases
Solution Approach 1:
The quantizer is segmented into multiple operational modes with different resolution levels. Instead of implementing all possible quantization levels simultaneously, the system segments the functionality into discrete resolution states (e.g., 3-level, 5-level, 7-level) that are activated sequentially according to the pseudo-random sequence, reducing the total number of comparators needed.
Solution Approach 2:
The quantizer structure is designed to be universal, capable of operating at multiple resolution levels using the same hardware resources. The same set of comparators can serve multiple quantization modes by selectively enabling different threshold combinations, eliminating the need for separate comparator sets for each resolution level.
Data Source
AI summary
A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log 2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.