Variable-Rate Block LDPC Encoding With a Single Parity Matrix
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Solution Overview
Problem
Current Low Density Parity Check (LDPC) codes in mobile communication systems are limited by their fixed coding rate, which restricts their ability to support variable coding rates necessary for high-speed, high-capacity data transmission, especially in environments with varying channel conditions.
Innovation Solution
A method and apparatus for encoding and decoding block LDPC codes with a variable coding rate, utilizing schemes such as shortening, removing, and puncturing to adjust the parity check matrix, allowing for flexible coding rates while minimizing coding complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed coding rate LDPC code is used, then the encoder structure is simple and reliable, but the system cannot adapt to variable channel conditions and high-speed data transmission requirements
Solution Approach 1:
The patent applies universality by designing a single encoder that can generate LDPC codes with multiple different coding rates. The encoder achieves this by selectively using different sub-matrices from a structured parity check matrix H, where H consists of an identity matrix I and a zero matrix O arranged in a specific pattern. This allows the same encoder hardware to support variable coding rates (e.g., 1/2, 2/3, 3/4) without requiring separate encoders for each rate, thus resolving the contradiction between adaptability and device complexity.
2Productivity
If the coding rate is increased to support high-speed transmission, then the data transmission capacity improves, but the error correction capability deteriorates
Solution Approach 1:
The patent applies parameter changes by systematically varying the coding rate parameter while maintaining a structured parity check matrix format. The parity check matrix H is constructed with specific patterns of identity matrices I and zero matrices O, where the arrangement and dimensions of these sub-matrices are adjusted according to the desired coding rate. This allows the system to optimize the balance between transmission rate and error correction capability for different channel conditions, rather than using a fixed coding rate that cannot adapt to varying requirements.
3Adaptability or versatility
If multiple encoders are used to support different coding rates, then the coding rate adaptability improves, but the device complexity and cost increase
Solution Approach 1:
The patent applies universality by designing a single encoder that can generate LDPC codes with multiple different coding rates. The encoder achieves this by selectively using different sub-matrices from a structured parity check matrix H, where H consists of an identity matrix I and a zero matrix O arranged in a specific pattern. This allows the same encoder hardware to support variable coding rates (e.g., 1/2, 2/3, 3/4) without requiring separate encoders for each rate, thus resolving the contradiction between adaptability and device complexity.
4Reliability
If conventional LDPC codes are used, then the error correction performance is good, but the coding rate is fixed and cannot be adjusted for different channel conditions
Solution Approach 1:
The patent applies parameter changes by systematically varying the coding rate parameter while maintaining a structured parity check matrix format. The parity check matrix H is constructed with specific patterns of identity matrices I and zero matrices O, where the arrangement and dimensions of these sub-matrices are adjusted according to the desired coding rate. This allows the system to optimize the balance between transmission rate and error correction capability for different channel conditions, rather than using a fixed coding rate that cannot adapt to varying requirements.
Data Source
AI summary
An apparatus and method for coding a block Low Density Parity Check (LDPC) code having a variable coding rate. The apparatus receives an information word and encodes the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix, depending on a coding rate to be applied when generating the information word into the block LDPC code.