Variable Rate Serial to Parallel Shift Register for Memory Redundancy
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Solution Overview
Problem
Conventional memory architectures face challenges in achieving high performance and capacity due to issues with neighboring field coupling and the inefficiencies of interleaving page architectures, which lead to read errors and reduced capacity in multi-state implementations.
Innovation Solution
A compact memory device with a bank of partitioned read/write stacks and a common processor that allows for parallel processing, along with column redundancy circuitry to manage bad columns, and variable rate shift registers to handle data transfer efficiently, reducing redundancy and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory architectures use interleaving page architecture to increase capacity, then memory capacity is improved, but read errors increase due to neighboring field coupling
Solution Approach 1:
The memory array is divided into multiple independent memory blocks, each with its own read/write stack. This segmentation isolates the magnetic fields of adjacent blocks, preventing field coupling between neighboring pages while maintaining high memory capacity through the multi-block architecture.
2Quantity of substance
If conventional architectures increase memory capacity through interleaving, then capacity is improved, but device complexity increases
Solution Approach 1:
Multiple memory blocks share common control circuitry and use a unified address decoding mechanism. The memory controller manages all blocks through standardized interfaces, reducing the overall system complexity despite the increased memory capacity provided by multiple blocks.
3Device complexity
If fixed rate data transfer is used in memory operations, then device complexity is reduced, but productivity decreases due to inefficiencies with bad columns
Solution Approach 1:
The data transfer rate between memory blocks and the processor is dynamically adjusted based on the presence of bad columns. When defective columns are detected, the transfer rate is automatically reduced to allow for proper error handling and data skipping, optimizing throughput without requiring complex preemptive control circuitry.
4Reliability
If redundancy is increased to handle bad columns, then reliability is improved, but device complexity and capacity are reduced
Solution Approach 1:
Each memory block contains self-diagnostic capability that automatically detects bad columns during initialization and operation. The block independently manages its own error correction and data skipping without requiring external intervention, reducing the overall system complexity while maintaining high reliability.
Data Source
AI summary
A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.