Variable Read Delay System for Memory Array Settling
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Solution Overview
Problem
Current memory read operations often result in data errors due to reading data before sense amplifier outputs have settled, leading to inefficient read times and increased error rates, as different memory cells take varying amounts of time to settle.
Innovation Solution
A variable read delay system that selects between a first and second sensing delay based on the specific memory cell, using selection logic and an error correction code to ensure accurate data retrieval, thereby reducing uncorrectable errors and optimizing read times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a worst case read time is used to ensure all memory cells have time to settle, then data accuracy is improved, but read operation speed deteriorates
Solution Approach 1:
The patent implements dynamic read timing adjustment by transitioning from a static worst-case read time to a variable read time that adapts to actual memory cell settling characteristics. The system uses read delay values stored in a delay portion to dynamically adjust the sense amplifier enable signal timing, allowing faster reads when memory cells settle quickly while maintaining data accuracy when settling takes longer.
Solution Approach 2:
The patent changes the timing parameter of the read operation by introducing variable read delay values that modify the sense amplifier enable signal timing. Different read delay values are stored in the delay portion and selected based on actual settling requirements, transforming the fixed timing parameter into a variable one that optimizes both speed and accuracy.
2Reliability
If a longer sensing delay is used to accommodate slow-settling memory cells, then data accuracy is improved, but average read time increases
Solution Approach 1:
The patent applies local quality by providing different sensing delay characteristics to different memory cells or groups of cells. The delay portion stores multiple read delay values that can be selectively applied to accommodate the specific settling characteristics of particular memory cells, rather than using a uniform delay for all cells.
Solution Approach 2:
The patent performs preliminary action by pre-storing multiple read delay values in the delay portion during manufacturing or initialization. These pre-computed delay values are then quickly retrieved and applied during read operations, avoiding the need for real-time calculation and enabling fast adaptation to different settling requirements.
3Adaptability or versatility
If read delay values are stored in a separate delay portion, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent merges the delay portion with the memory array structure, integrating the storage of read delay values into the existing memory architecture. This combining approach allows the system to gain adaptability through variable delay values while minimizing the increase in overall device complexity by reusing existing structural elements.
Solution Approach 2:
The delay portion serves multiple functions: it stores read delay values for timing adjustment, and can potentially store other operational parameters. This multi-functionality increases adaptability while amortizing the complexity cost across multiple uses of the same structural element.
Data Source
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AI summary
A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.