Variable Read Threshold Nonvolatile Memory

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Solution Overview

Problem

Nonvolatile memory systems face errors during data read due to voltage shifts, leading to incorrect data recovery, especially as the memory ages, and existing Error Correction Codes (ECCs) struggle to maintain reliable data recovery with increasing errors, requiring complex hardware and high computational costs.

Innovation Solution

A flash memory system that maps memory states to different threshold windows over time, using a reading circuit to compare threshold voltages to predetermined voltages for accurate data retrieval, and an adjustment circuit to modify these voltages based on ECC decoder information, allowing for more precise state discrimination and error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional Error Correction Codes (ECCs) are used to detect and correct erroneous bits, then data integrity can be maintained, but the hardware complexity and computational cost increase significantly

Engineering Contradiction:
Improvedata integrityVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parameter of read threshold voltages dynamically based on memory cell age and error patterns. Instead of using complex ECC hardware, the system adjusts the voltage threshold parameter to optimize reading accuracy for different memory states, thereby maintaining data integrity with simpler circuitry.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The read threshold voltage is made dynamic rather than static. The threshold adapts based on the memory cell's program/erase cycle count and observed error patterns, allowing the system to respond to degradation over time without requiring increasingly complex error correction hardware.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If fixed read threshold voltages are used throughout memory operation, then the reading circuit design is simple, but data recovery reliability deteriorates as memory ages and voltage shifts occur

Engineering Contradiction:
Improvereading circuit designVSAvoiddata recovery reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The read threshold voltage transitions from a fixed value to a dynamic parameter that changes based on memory cell characteristics. The system monitors memory cell age and error patterns, then adjusts the threshold voltage accordingly, maintaining high data recovery reliability throughout the memory's operational life.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback by monitoring error patterns and memory cell state, then using this information to adjust read threshold voltages. This closed-loop approach ensures that the reading circuit maintains optimal performance despite memory degradation, without requiring a completely redesign of the reading circuit architecture.

Inventive Principle:
Principle #23Feedback

3Device complexity

If a single threshold window is used for all memory states, then the mapping is simple, but state discrimination precision decreases when likelihood distributions widen with use

Engineering Contradiction:
Improvethreshold mappingVSAvoidstate discrimination precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the threshold window into multiple sub-windows or adjusts the threshold positions within the window based on memory cell state and age. This segmentation allows for more precise discrimination between adjacent memory states even as their probability distributions widen due to wear and usage.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7558109B2Nonvolatile memory with variable read threshold
Publication Date: 2009.07.07 SANDISK TECHNOLOGIES LLC
  • US7558109B2 patent drawing
  • US7558109B2 patent drawing
  • US7558109B2 patent drawing

AI summary

Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. Individual memory states are mapped to sub-ranges that are made wider, reducing errors.