Variable Read Voltage Adjustment for 3D NAND Neighbor Interference
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Solution Overview
Problem
In semiconductor memory devices, particularly in 3D NAND flash memory structures, neighbor word line interference causes shifts in threshold voltage (Vth) distributions, leading to read errors and widened Vth distributions, which complicates the programming and reading processes.
Innovation Solution
Implementing a multi-pass program operation with a variable read voltage (Vread) that increases with verify voltage during the final pass, allowing for optimal adjustment based on data states and program-erase cycles to compensate for neighbor word line interference, thereby achieving a narrow final Vth distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed read voltage is applied to adjacent word lines during verify tests, then the programming process is simple to implement, but neighbor word line interference causes threshold voltage distribution to widen and read errors increase
Solution Approach 1:
The patent applies dynamic adjustment of read voltage to adjacent word lines based on the verify voltage level and program-erase cycle count. The read voltage transitions from fixed to variable, increasing with each verify voltage level to compensate for neighbor word line interference. This dynamic approach narrows the threshold voltage distribution and reduces read errors while maintaining programming accuracy across multiple passes.
2Measurement precision
If verify voltage is increased to improve programming accuracy, then data state verification becomes more precise, but neighbor word line interference increases causing threshold voltage shifts and read errors
Solution Approach 1:
The patent applies preliminary counter-action by increasing the read voltage on adjacent word lines before and during verify tests at higher verify voltage levels. This preemptive measure compensates for the expected neighbor word line interference that occurs when verifying higher data states, preventing threshold voltage shifts and maintaining measurement precision without sacrificing accuracy.
3Manufacturing precision
If multi-pass programming is used to achieve narrow threshold voltage distribution, then programming accuracy is improved, but the number of program-erase cycles increases leading to more cumulative interference
Solution Approach 1:
The patent changes the read voltage parameter dynamically based on the program-erase cycle count and verify voltage level. As multiple passes are executed, the read voltage is adjusted to compensate for cumulative neighbor word line interference, maintaining narrow threshold voltage distribution throughout the multi-pass programming process. This parameter adaptation enables accurate programming while accounting for time-related degradation from repeated cycles.
Data Source
AI summary
Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.