Variable-Reference DDS PLL for Low-Spur Edge Placement
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Solution Overview
Problem
Direct digital synthesizers (DDS) face challenges in achieving improved spurious performance due to limitations in the resolution of digital to analog converters (DAC) and digital to time converter (DTC) systems, primarily caused by quantization errors and mismatch errors in the tapped delay line, which result in spurious frequency components in the output.
Innovation Solution
The solution involves using a phase lock loop (PLL) feedback loop with a fractional divider to minimize quantization errors by adjusting the PLL reference frequency based on normalized quantization error and providing independently tunable delay elements in the delay line to reduce mismatch errors, allowing for finer tuning and compensation of delay line errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the tapped delay line is increased to improve edge placement accuracy, then the spurious performance improves, but the device complexity and manufacturing difficulty increase due to process technology limitations
Solution Approach 1:
The patent applies dynamics by making the delay line resolution adjustable rather than fixed. The tapped delay line can dynamically change its effective resolution based on the reference frequency, allowing the system to optimize edge placement accuracy for different operating conditions without requiring a permanently complex high-resolution structure.
Solution Approach 2:
The patent changes the parameter of delay line resolution from a fixed physical constraint to a variable parameter controlled by the reference frequency. By adjusting the reference frequency, the effective resolution of the delay line changes, allowing the system to achieve high edge placement accuracy when needed while avoiding the constant complexity of a permanently high-resolution design.
2Measurement precision
If the number of taps in the delay line is increased to improve resolution, then the edge placement accuracy improves, but the mismatch errors between transistors cause unequal delays and degrade performance
Solution Approach 1:
The patent uses feedback by monitoring the reference frequency and adjusting the operation of the tapped delay line accordingly. The system detects conditions that would lead to quantization errors and mismatch errors, and uses this information to adjust the effective resolution and timing, compensating for transistor mismatch variations.
Solution Approach 2:
The system dynamically adjusts the effective resolution of the delay line based on the reference frequency. Rather than using a fixed high-number-of-taps configuration that exacerbates mismatch errors, the system adapts the number of effective taps to match the reference frequency, reducing the impact of transistor mismatch while maintaining adequate resolution.
3Device complexity
If the reference frequency is fixed to simplify the system, then the device complexity decreases, but quantization errors occur when the reference frequency does not divide evenly into the output frequency
Solution Approach 1:
The patent makes the reference frequency dynamic rather than fixed. The reference frequency can be adjusted to values that are integer divisors of the desired output frequency, eliminating quantization errors. This dynamic adjustment allows the system to maintain high frequency accuracy without requiring an excessively complex frequency synthesis system.
Solution Approach 2:
The system changes the reference frequency parameter dynamically based on the desired output frequency. By selecting reference frequencies that are appropriate divisors of the output frequency, the system eliminates quantization errors while keeping the frequency control mechanism relatively simple.
Data Source
AI summary
Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.