Variable-Reference Power-On Reset Circuit for Stable Memory Startup
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in performing stable power-on reset and word line discharge operations, particularly during power up and power down periods, due to variations in external power supply voltage levels and the need for accurate detection signals.
Innovation Solution
A power-on reset circuit is designed with a voltage dividing circuit, output node control circuit, and buffer circuit to generate and control power-on reset signals based on external power supply voltage levels, and an external voltage detecting unit to ensure stable word line discharge during power down, using different detection reference levels for power up and power down operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed reference voltage is used for power-on reset detection, then the circuit structure is simple, but the detection accuracy deteriorates under varying power supply conditions
Solution Approach 1:
The patent applies dynamics by making the reference voltage variable rather than fixed. The reference voltage is dynamically adjusted based on whether the device is in power-up or power-down mode, allowing the detection threshold to adapt to different operating conditions and improve detection accuracy without excessive complexity
Solution Approach 2:
The patent changes the parameter of reference voltage from a static value to a dynamic value that differs between power-up and power-down periods. This parameter change enables accurate detection across varying power supply conditions while maintaining reasonable circuit complexity through controlled variability
2Reliability
If different detection reference levels are used for power up and power down operations, then the operational stability is improved, but the circuit complexity increases
Solution Approach 1:
The patent segments the detection operation into two distinct modes: power-up detection and power-down detection. Each mode uses its own reference voltage level, allowing optimized detection for each operational phase while maintaining overall system reliability without excessive complexity
Solution Approach 2:
The circuit dynamically switches between different reference voltage levels based on the operational state (power-up or power-down). This dynamic adaptation improves operational stability by using appropriate reference levels for each phase while managing complexity through state-based control
3Measurement precision
If the reference voltage level is adjusted dynamically, then the detection accuracy under varying power conditions is improved, but the control complexity increases
Solution Approach 1:
The patent changes the reference voltage parameter dynamically based on operational state. By linking the reference voltage selection to the power state (up or down), the system achieves accurate detection under varying power conditions while keeping the control mechanism manageable through state-based parameter selection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables stable power-on reset and word line discharge operations by accurately controlling power-on reset signals and detection levels, reducing errors and ensuring reliable semiconductor memory device performance across varying power supply conditions.
Implementation Method 1
a voltage dividing circuit configured to divide an external power supply voltage to output a reference voltage
Data Source
AI summary
Provided herein are a power-on reset circuit and a semiconductor memory device including the same. The power-on reset circuit may include: a voltage dividing circuit suitable for dividing an external power supply voltage to output a reference voltage, an output node control circuit suitable for controlling a potential level of an output node to an external power supply voltage level or a ground power supply voltage level in response to the reference voltage, and a buffer circuit suitable for buffering the potential level of the output node to output a power-on reset signal. In the voltage dividing circuit, a potential level of the reference voltage in a power up period is different from a potential level of the reference voltage in a power down period.