Variable-Resistance Storage Circuits With Analog-Buffered Read Paths
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Solution Overview
Problem
Existing storage circuits face challenges in miniaturization and large-scaling while maintaining read speed due to differences in wiring driving times and increased capacitance, which can lead to read disturb and slower read speeds.
Innovation Solution
A storage circuit design with a memory cell array using variable resistance type elements, resistance-voltage conversion circuits, reference circuits, and analog buffer circuits to equalize current driving capabilities and reduce wiring capacitance, allowing for faster signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wiring is thickened to reduce resistance, then wiring resistance is reduced, but wiring capacitance increases
Solution Approach 1:
The patent divides the long bit line into multiple segments by inserting buffer circuits at intermediate positions. This segmentation reduces the effective capacitance that any single driving transistor must charge, thereby reducing wiring driving time without requiring thicker wiring throughout the entire line.
Solution Approach 2:
Buffer circuits are introduced as intermediary elements between the memory cell array and the sense amplifier. These buffers act as intermediate driving stages that can charge the bit line capacitance more efficiently, reducing the overall wiring driving time without increasing the capacitance of the main bit line wiring.
2Speed
If on-resistance of read load transistors is made small to charge wiring capacitance rapidly, then wiring driving time is reduced, but read current becomes large causing read disturb
Solution Approach 1:
By segmenting the bit line and inserting buffer circuits, the patent enables the use of moderate-sized read load transistors that do not cause read disturb, while still achieving fast wiring driving through the buffered stages that rapidly charge the segmented line segments.
Solution Approach 2:
Buffer circuits serve as intermediary driving stages that can provide the necessary current to charge wiring capacitance rapidly without requiring the read load transistors to be oversized, thereby preventing read disturb while maintaining fast wiring driving time.
3Area of stationary object
If memory cells are miniaturized, then storage circuit size is reduced, but on-resistance of read load transistors increases slowing down read speed
Solution Approach 1:
The patent compensates for the increased on-resistance of read load transistors in miniaturized memory cells by inserting buffer circuits that provide additional driving strength. This segmentation allows the use of smaller memory cells while maintaining fast read speed through the buffered driving stages.
Solution Approach 2:
Buffer circuits act as intermediary elements that compensate for the increased on-resistance of read load transistors in miniaturized memory cells, providing the necessary current driving capability to maintain fast read speed despite the smaller device dimensions.
4Speed
If a sense amplifier is disposed for each bit line to increase read speed, then read speed is improved, but wiring for transmitting reference voltage becomes long increasing wiring driving time
Solution Approach 1:
The patent inserts buffer circuits at strategic positions along the bit lines to create multiple driving stages. This segmentation reduces the effective wiring driving time for reference voltage transmission to sense amplifiers, enabling faster read speeds without requiring excessively long reference voltage wiring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables miniaturization and large-scaling of storage circuits with increased read speed by optimizing current driving capabilities and reducing wiring capacitance through analog buffer circuits and reference circuits.
Implementation Method 1
a memory cell array including a matrix of memory cells each of which includes a variable resistance type element, the variable resistance type element having a resistance value changing in at least two steps
Implementation Method 2
a resistance-voltage conversion circuit to convert a resistance value of a memory cell to be read in the memory cell array to a data voltage
Data Source
AI summary
A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTj to convert a resistance value of a memory cell MCij to be read to a data voltage, a reference circuit and RTR to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTj and a first input terminal of the sense amplifier or between the reference circuit and RTR and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.