Variable Resistance Pattern Capping for Memory Integrity
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Solution Overview
Problem
Existing electronic devices face challenges in achieving miniaturization, low power consumption, and high performance while maintaining variable resistance patterns across regions with height differences, leading to issues with wet chemical penetration and pattern integrity in memory circuits.
Innovation Solution
The implementation of a semiconductor memory device with a substrate having distinct regions, interlayer dielectric layers, conductive patterns, and a capping layer with non-metallic materials to prevent wet chemical penetration, ensuring the integrity of variable resistance patterns, particularly using an MTJ structure and a capping layer composed of amorphous semiconductor materials or metal oxides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used without specialized capping layers, then manufacturing simplicity is maintained, but wet chemical penetration occurs in regions with height differences, compromising pattern integrity
Solution Approach 1:
The patent applies different capping layer configurations to different regions of the substrate. First regions (with height differences) receive a capping layer with non-metallic material specifically designed to prevent wet chemical penetration, while second regions (without height differences) may use conventional capping structures. This localized approach ensures pattern integrity where needed without unnecessarily complicating the entire device structure.
Solution Approach 2:
The capping layer is constructed using composite materials combining metallic and non-metallic layers. The non-metallic material layer (such as silicon oxide, silicon nitride, or silicon oxynitride) is specifically incorporated to provide chemical resistance against wet etchants, while metallic layers provide electrical conductivity. This composite structure addresses both the need for chemical protection and electrical functionality.
2Manufacturing precision
If regions with height differences are processed using standard wet chemical methods, then manufacturing simplicity is maintained, but wet chemical penetration occurs compromising variable resistance pattern integrity
Solution Approach 1:
The capping layer with non-metallic material is formed beforehand (prior to wet chemical processing steps) on regions with height differences. This preliminary protective layer prevents wet chemical penetration during subsequent fabrication steps, ensuring that variable resistance patterns are formed with high precision without being compromised by chemical etching or contamination.
3Productivity
If miniaturization is pursued to achieve lower power consumption and higher performance, then device density improves, but maintaining variable resistance patterns across height differences becomes more difficult
Solution Approach 1:
As devices are miniaturized and integrated at higher densities, the patent applies the specialized capping layer with non-metallic material selectively to first regions where height differences exist, even at scaled dimensions. This ensures that variable resistance patterns maintain their integrity and stability throughout the miniaturized device structure, allowing high device density without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the formation of reliable variable resistance patterns across regions with height differences, preventing wet chemical penetration and maintaining pattern integrity, thus enhancing the performance and reliability of memory devices in electronic devices.
Implementation Method 1
a capping layer pattern formed over the variable resistance pattern and having a sidewall aligned with the variable resistance pattern while including a non-metallic material which prevents a penetration of a wet chemical
Data Source
AI summary
An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.