Variable Resistance Cell Array for Neuromorphic Sum-of-Products
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Solution Overview
Problem
Existing neuromorphic computing and machine learning systems face challenges in implementing energy-efficient sum-of-products operations due to high power consumption in large arrays, which is exacerbated by the need for numerous inputs and outputs.
Innovation Solution
A device comprising an array of variable resistance cells with programmable threshold transistors and resistors in parallel, where the resistance is controlled by voltage applied to the transistor's control gate, allowing for voltage sensing to limit current and reduce power consumption, implemented in 2D and 3D arrays with buried implant resistors for compact layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large arrays are used to perform many operations in parallel, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent replaces traditional current-based sensing with voltage sensing in the sum-of-products array. This substitution fundamentally changes the sensing mechanism from measuring current (which requires high current drive and consumes power) to measuring voltage (which can be done with high impedance inputs that consume minimal current), thereby reducing power consumption while maintaining high productivity in large parallel arrays
Solution Approach 2:
The patent changes the operating parameter from current-mode to voltage-mode operation. By using voltage sensing instead of current sensing, the system can operate large parallel arrays with much lower power consumption, as voltage measurements can be performed with high-impedance buffers that draw minimal current, thus resolving the contradiction between array size/productivity and power consumption
2Productivity
If more inputs and outputs are added to increase computation capacity, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal voltage sensing architecture that can handle any number of inputs and outputs through the same basic sensing mechanism. The voltage sensing approach with high-impedance buffers allows the same circuit topology to scale to large arrays without proportionally increasing output complexity, as each column can be sensed independently with minimal interference, enabling computation capacity expansion without linearly increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient sum-of-products operations by reducing power consumption and allowing for compact, high-density arrays, improving the energy efficiency and scalability of neuromorphic computing systems.
Implementation Method 1
a programmable threshold transistor and a resistor connected in parallel. The device can be operated so that an input voltage applied to the transistor and the programmable threshold of the transistor can represent variables of sum-of-products operations. The variable resistance of each variable resistance cell, in embodiments described herein, is a function of a voltage applied to the control gate of the programmable threshold transistor in the cell
Implementation Method 2
The device in some embodiments includes a voltage sensing sense amplifier, configured to sense the voltage generated by the variable resistance cells, as a function of an applied current and the resistance of the variable resistance cells. In this manner, the magnitude of the current generated to produce the sum-of-products result can be limited or fixed, reducing the power consumption
Implementation Method 3
embodiments described herein can implement the resistor as a buried implant resistor within the layout footprint of a single variable threshold transistor, in effect making an array of one transistor (1T) cells, for a very compact layout configured for sum-of-products operations with voltage sensing
Data Source
AI summary
An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.