Variable Resistance Decoder Circuits for Read Disturb Mitigation
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Solution Overview
Problem
In storage devices like phase change memory, read operations can cause current spikes that resemble write operations, leading to undesirable changes in stored data, known as read disturbs or false writes, due to the similarity between memory cell currents during read and write operations.
Innovation Solution
The implementation of variable resistance circuits and transistor configurations that adjust resistance levels and gate voltages to minimize the width of current spikes during read operations, thereby reducing the likelihood of false writes by setting resistances to high levels before turn-on and adjusting to low levels post-spike, using decoder controllers to manage these changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If variable resistance circuits adjust resistance to high levels before turn-on and low levels post-spike, then current spike width is minimized and false writes are reduced, but device complexity increases
Solution Approach 1:
The variable resistance circuit is configured to set resistance to a high level before the memory cell turn-on event during read operations. This preliminary high resistance state limits the current spike width at its source, preventing excessive current from reaching the memory cell and causing false writes, while the resistance is subsequently adjusted to a low level after the spike event
Solution Approach 2:
The decoder circuit incorporates dynamically adjustable resistance elements that can switch between high and low resistance states based on the operational phase. During read operations, resistance transitions from high (pre-spike) to low (post-spike), while during write operations, the resistance remains low to allow full current flow, enabling the same circuit to serve multiple functions with different characteristics
2Reliability
If gate voltages are adjusted to control current spike width, then read disturb is minimized, but control complexity increases
Solution Approach 1:
The decoder controller dynamically adjusts gate voltage parameters of transistor circuits based on the operational context. During read operations, gate voltages are modulated to control the turn-on timing and current spike characteristics of select transistors, while during write operations, standard gate voltage levels are applied. This parameter adjustment enables precise control over current flow without requiring separate dedicated circuits
3Loss of energy
If resistance is increased to limit current spike, then energy transfer to memory cell is reduced, but this may affect write operation performance
Solution Approach 1:
The variable resistance circuit operates in distinct temporal phases: during read operations, resistance is set to high levels during the critical pre-spike period to limit energy transfer, then transitions to low levels after the spike event. During write operations, the resistance remains in a low state throughout the operation. This time-dependent resistance modulation ensures energy limitation only when needed for read protection
Solution Approach 2:
The circuit establishes high resistance levels before the current spike event during read operations, preliminarily preventing excessive energy transfer to the memory cell. This preliminary protective action is temporarily applied only during read operations and is removed during write operations to ensure full write performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the width of current spikes and reduces the energy transferred to memory cells, thereby minimizing the occurrence of false writes and maintaining data integrity during read operations.
Implementation Method 1
The variable resistance circuit is configured to: set an associated resistance to a high resistance level in advance of the memory cell turning on; and adjust the associated resistance from the high resistance level to a low resistance level in response to an end time of an initial turn-on time period
Implementation Method 2
The transistor circuit is configured to: receive a voltage, and set an effective gate-to-source voltage of the transistor circuit to reduced voltage levels configured to reduce a width of a spike portion of a memory cell current
Data Source
AI summary
In a memory system, variable resistance circuits, such as transistor circuits, in the word line and bit line decoders are set during bias line set times and/or prior to turn-on times of read operations to increased resistance levels. The variable resistance circuits are kept at the increased resistance levels during an initial turn-on time period during which a selected memory cell may conducts a current spike. The increased resistance levels of the variable resistance circuit may operate to reduce or limit the width of the current spike. In response to the initial turn-on time period ending, the variable resistance circuits are set back to low resistance levels to facilitate subsequent sense results detection events and program operations.