Variable Resistance Memory Diode Etching Segmentation
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices using cross-point cells face issues with characteristic deterioration and damage due to reactive ion etching, leading to degradation of diode and variable resistance element performance.
Innovation Solution
A nonvolatile semiconductor memory device design featuring a common variable resistance film between diodes, where the diodes are formed without using reactive ion etching, preventing damage and maintaining device characteristics, and a method of manufacturing involving specific semiconductor layer formations and chemical processes to ensure high aspect ratio diodes without pattern destruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reactive ion etching is used to form memory cells with thick diode films for reverse-bias leak resistance, then leak resistance is improved, but the pattern is destroyed due to high aspect ratio
Solution Approach 1:
The patent segments the etching process into multiple steps with different etching conditions. A first etching process forms the diode pattern with moderate aspect ratio, then a second etching process forms the variable resistance element pattern. This segmentation allows each etching step to operate under optimized conditions, preventing pattern destruction while achieving the required thick diode film for leak resistance.
Solution Approach 2:
The patent performs preliminary patterning of the diode structure before forming the variable resistance element. The diode pattern is first formed with appropriate thickness for leak resistance, then the variable resistance element is subsequently formed. This preliminary action ensures that the diode structure is already in place with correct dimensions before the second etching process, avoiding pattern destruction.
2Ease of manufacture
If reactive ion etching is used to etch the variable resistance element, then device characteristic degradation occurs due to sidewall damage and dangling bonds
Solution Approach 1:
The patent changes the etching parameters between the first and second etching processes. The first etching process uses parameters optimized for forming the diode pattern, while the second etching process uses different parameters optimized for forming the variable resistance element pattern with minimal sidewall damage. This parameter change reduces dangling bonds and maintains device characteristics while still enabling cross-point cell array formation.
3Area of moving object
If scale reduction is performed on the device, then memory cell size is reduced, but the aspect ratio increases causing pattern destruction
Solution Approach 1:
The patent segments the fabrication process into distinct etching steps that are not limited by the aspect ratio constraints of a single etching process. By forming the diode pattern first and then the variable resistance element pattern separately, each step can be optimized for the scaled dimensions without creating excessively high aspect ratios that would lead to pattern destruction.
Data Source
AI summary
A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.