Multi-Layered Variable Resistance Element Stacking for Chip Area Reduction
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Solution Overview
Problem
The challenge is to reduce the chip area of semiconductor devices like FPGAs, where the layout area for variable resistance elements is large when arranged in a plane direction, and multi-layering complicates the placement of these elements, increasing the chip area further.
Innovation Solution
The semiconductor device configures connection blocks and switch blocks using multi-layered variable resistance elements arranged along a stacking direction, optimizing the layout by omitting unnecessary connection points and using two types of unit configurations to maintain logical line connections, thereby reducing the overall chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If variable resistance elements are arranged in a plane direction, then the device structure is simple, but the layout area becomes large
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional stacked arrangement of variable resistance elements. Multiple layers are stacked vertically with connection blocks positioned between layers to establish electrical connections, thereby reducing the footprint area while maintaining device functionality.
2Area of stationary object
If multi-layering is used to reduce area, then the layout area is reduced, but the placement complexity increases
Solution Approach 1:
The device is segmented into distinct functional layers: variable resistance element layers, connection blocks, and bit line layers. Each layer has a specific function and is independently designed, which simplifies the overall placement process despite the three-dimensional structure. Connection blocks act as intermediaries that manage connections between layers.
Solution Approach 2:
Connection blocks serve as intermediary components between variable resistance elements in different layers. These connection blocks simplify the placement process by providing standardized interfaces and connection points, reducing the complexity of establishing electrical connections across multiple layers.
3Area of stationary object
If connection points are omitted to reduce area, then the layout area is reduced, but the connection reliability may be affected
Solution Approach 1:
Connection blocks are designed with multi-functionality, serving both as connection points for variable resistance elements and as routing nodes for bit lines. This universal design allows for fewer connection points while maintaining all necessary electrical connections, thereby reducing area without compromising reliability.
Data Source
AI summary
According to one embodiment, in a semiconductor device, a connection block includes multiple unit configurations, in each of which a first line extends along a first direction. A second line is placed above the first line and extends along a second direction which intersects with the first direction. A first variable resistance element has one end electrically connected to the first line and another end electrically connected to the second line. The third line is placed above the second line and extends along the first direction. A second variable resistance element has One end electrically connected to the second line and another end electrically connected to the third line. A fourth line is placed above the third line. The fourth line extends along the second direction. A third variable resistance element has one end electrically connected to the third line and another end electrically connected to the fourth line.