Variable Resistance Layer as Gate Insulator in Semiconductor Memory
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the increased size and degraded operation characteristics due to the need for interconnections and contacts between memory arrays and peripheral circuits, which complicates the structure and increases resistance, making it difficult to accurately control resistive memory devices.
Innovation Solution
A semiconductor device is designed with a stacked structure where a variable resistance layer acts as both a gate insulating layer and a channel layer, integrated with a transistor region, allowing for reduced chip size by eliminating the need for separate interconnections and contacts, and utilizing oxide layers with oxygen vacancies to change resistance for data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate contacts and interconnections are formed to connect memory arrays to peripheral circuits, then the memory device can be fabricated with conventional structures, but the device size increases and operation characteristics degrade
Solution Approach 1:
The patent merges the memory array and peripheral circuits into a single integrated structure where memory cells are formed directly over the peripheral circuit substrate. This eliminates the need for separate contacts and interconnections, reducing device area while maintaining conventional fabrication compatibility.
Solution Approach 2:
The substrate serves multiple functions: it acts as both the memory array substrate and the peripheral circuit substrate. This multi-functionality eliminates the need for separate substrates and their associated interconnections, thereby reducing overall device size.
2Ease of manufacture
If separate contacts and interconnections are formed to connect memory arrays to peripheral circuits, then the memory device can be fabricated with conventional structures, but the structure becomes complicated and space is increased
Solution Approach 1:
The patent combines the memory array formation and peripheral circuit formation into a single integrated process flow. By forming memory cells directly over the peripheral circuit substrate, the complex multi-layer interconnection structure is eliminated, simplifying the overall device architecture.
3Productivity
If design rule decreases, then the integration density increases, but the critical dimension of interconnection decreases thus increasing resistance
Solution Approach 1:
The patent extracts the interconnection function from the conventional separate contact structure and integrates it directly into the memory cell formation process. Memory cells are formed with direct electrical connection to peripheral circuits, eliminating long interconnection paths and their associated resistance issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces chip size, and enhances the operation characteristics of high-capacity memory devices by integrating memory and peripheral circuits within a single memory block, thereby minimizing the complexity of interconnections and improving resistance control.
Implementation Method 1
The variable resistance layer may include an oxide layer, and the oxide layer may include a plurality of oxygen vacancies
Data Source
AI summary
A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.