Variable Resistance Layer Sharing for Memory Integration
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density and efficient data storage with low power consumption, particularly in miniaturized electronic devices, where existing technologies struggle to optimize the contact area between variable resistance elements and electrodes, affecting operational characteristics.
Innovation Solution
The proposed electronic device incorporates a semiconductor memory with a variable resistance layer interposed between pillar electrodes, where a group of first pillar electrodes contacts one variable resistance layer surrounding a second pillar electrode, and vice versa, allowing multiple memory cells to share a single variable resistance layer, enhancing integration density and operational characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional memory structure with separate variable resistance elements for each memory cell is used, then each memory cell has dedicated storage capability, but the integration density is limited due to the large area required for each cell
Solution Approach 1:
The patent merges multiple memory cell functions into a single variable resistance layer by having multiple first pillar electrodes contact the same variable resistance layer surrounding a second pillar electrode. This sharing mechanism allows one variable resistance layer to serve multiple memory cells, significantly increasing integration density while reducing the area required per memory cell.
Solution Approach 2:
The variable resistance layer is designed to perform multiple functions simultaneously by being contacted by groups of first pillar electrodes that belong to different memory cells. This universal variable resistance layer enables efficient data storage across multiple memory cells, improving both integration density and operational characteristics.
2Reliability
If the contact area between electrodes and variable resistance layers is increased to improve operational characteristics, then data storage efficiency improves, but the area occupied by each memory cell increases
Solution Approach 1:
By merging the contact areas of multiple memory cells into a single variable resistance layer, the patent achieves sufficient contact area for reliable operation without requiring proportionally larger individual cell areas. The shared variable resistance layer provides adequate contact surface for multiple first pillar electrodes, maintaining operational reliability while conserving space.
Solution Approach 2:
The patent utilizes vertical stacking of pillar electrodes and variable resistance layers to increase contact area without proportionally increasing the planar footprint. By arranging memory cells in three-dimensional space with multiple layers, the system achieves improved operational characteristics through enhanced contact area while maintaining high integration density.
Data Source
AI summary
An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first pillar electrodes spaced apart from each other, a plurality of second pillar electrodes spaced apart from each other, each second pillar electrode being spaced apart from adjacent first pillar electrodes, and a plurality of variable resistance layers enclosing sidewalls of corresponding second pillar electrodes, respectively, wherein a group of adjacent first pillar electrodes is in contact with one variable resistance layer, and a group of adjacent variable resistance layers is in contact with one first pillar electrode.