Variable Resistance Layer Sharing for Semiconductor Memory Fabrication
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Solution Overview
Problem
The increasing complexity and cost of manufacturing semiconductor memories due to their miniaturization and integration pose challenges in the fabrication process.
Innovation Solution
A semiconductor device and method utilizing a sidewall spacer fabrication process to form a memory cell with a variable resistance layer between two conductive layers, reducing the number of manufacturing processes and costs by sharing the resistance layer between two memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor memories are miniaturized and integrated to increase density, then storage capacity increases, but manufacturing complexity and costs increase
Solution Approach 1:
The patent merges two memory cell structures by sharing a single variable resistance layer between two memory cells. The first and second memory cells share the common variable resistance layer, which is formed between a first conductive layer and a second conductive layer. This merging approach increases storage capacity while reducing the number of manufacturing steps compared to forming separate resistance layers for each cell.
Solution Approach 2:
The variable resistance layer serves multiple functions simultaneously: it acts as the resistance element for the first memory cell and the resistance element for the second memory cell. This multi-functionality allows a single layer to support multiple memory cells, reducing overall device complexity while maintaining high storage capacity.
2Quantity of substance
If semiconductor memories are miniaturized and integrated to increase density, then storage capacity increases, but manufacturing costs increase
Solution Approach 1:
The patent merges two memory cell structures by sharing a single variable resistance layer between two memory cells. The first and second memory cells share the common variable resistance layer, which is formed between a first conductive layer and a second conductive layer. This merging approach increases storage capacity while reducing the number of manufacturing steps compared to forming separate resistance layers for each cell.
3Ease of manufacture
If sidewall spacer fabrication process is used to form electrodes, then manufacturing process is simplified, but precise control of electrode dimensions is required
Solution Approach 1:
The patent uses sidewall spacers as preliminary structures that are formed on the variable resistance layer before the final electrode formation. These spacers define the boundaries and dimensions of the electrodes, allowing precise dimensional control through the spacer thickness rather than requiring direct patterning of the electrodes themselves. This preliminary action simplifies the overall fabrication process while maintaining precision.
Data Source
AI summary
A semiconductor device includes a first conductive layer extending in a first direction, a second conductive layer extending in a second direction and disposed over the first conductive layer, the first and second directions being substantially perpendicular to each other, and a variable resistance layer disposed over the first conductive layer, the variable resistance layer extending in the second direction. An upper portion of the variable resistance layer is disposed between lower portions of two neighboring second conductive layers including the second conductive layer.