Variable Resistance Memory Device 3D Stacking Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the expensive equipment required for fine pattern formation, hindering the increase in memory cell density and overall integration, which is crucial for high-performance and low-cost semiconductor devices.
Innovation Solution
A variable resistance memory device with three-dimensionally arranged memory cells, featuring conductive lines and memory cells positioned at the same level on a substrate, allowing for horizontal and vertical stacking, thereby increasing integration density without the need for expensive equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited due to area occupation by unit memory cells
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking. Multiple memory cells are stacked vertically along the third direction (perpendicular to substrate), with conductive lines extending in multiple directions to connect cells at different levels. This dimensional change dramatically increases integration density without requiring proportionally smaller unit cell areas.
2Quantity of substance
If expensive processing equipment is used to increase pattern fineness, then integration of two-dimensional devices can be increased, but manufacturing cost increases significantly
Solution Approach 1:
Instead of relying on expensive equipment to create finer two-dimensional patterns, the invention uses vertical stacking to achieve higher integration. The third-dimensional arrangement allows memory cells to be stacked above each other, connected by conductive lines extending vertically and horizontally, thereby increasing density through spatial arrangement rather than pattern miniaturization.
Solution Approach 2:
The patent employs selective doping regions (first and second doped regions with different conductivity types) within the semiconductor layer to create localized functional areas. This allows different regions to perform different functions (e.g., source, drain, channel) while maintaining a relatively simple overall structure that can be fabricated with standard processing equipment.
3Quantity of substance
If three-dimensionally arranged memory cells are implemented, then integration density is increased, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is divided into repeating modular units. Each memory cell consists of a semiconductor region with source and drain electrodes, separated by insulating layers. These modular units are stacked vertically and connected through conductive lines, allowing the complex three-dimensional structure to be built from simple, repeatable building blocks that can be fabricated using standard processing techniques.
Data Source
AI summary
Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.