Variable Resistance Memory Air Gap Insulation

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Solution Overview

Problem

As variable resistance memory devices shrink, parasitic capacitance between conductive lines or memory cells becomes problematic, requiring effective methods to reduce this capacitance to maintain device performance.

Innovation Solution

The implementation of an air gap in the insulation layer structure between conductive lines, specifically designed to overlap neither the conductive lines nor the memory units, reduces parasitic capacitance by ensuring the air gap's top is lower than the lower surfaces of the conductive lines, preventing electrical shorts and enhancing device efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the size of variable resistance memory device is decreased, then the integration density is improved, but the parasitic capacitance between conductive lines or memory cells increases

Engineering Contradiction:
Improvedevice sizeVSAvoidparasitic capacitance
Core Design Contradiction:
Area of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces air gaps that segment the insulation layer structure into distinct regions. These air gaps physically divide the continuous insulation material, creating isolated zones that reduce capacitive coupling between adjacent conductive lines and memory cells, thereby reducing parasitic capacitance while maintaining device miniaturization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The air gap acts as an intermediary layer between conductive lines and memory cells. By introducing this intermediate space filled with air (having lower dielectric constant than solid insulation), the patent reduces the electric field coupling between adjacent structures, effectively lowering parasitic capacitance without increasing device footprint

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If an air gap is formed in the insulation layer structure, then the parasitic capacitance is reduced, but the risk of electrical short between conductive lines increases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidelectrical short prevention
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent strategically positions the air gap at a specific vertical depth within the insulation layer structure, creating a three-dimensional configuration. The air gap extends only partially through the insulation thickness and is located in regions that do not vertically overlap with conductive lines, utilizing the vertical dimension to maintain electrical isolation while achieving capacitance reduction in the horizontal plane

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The air gap is not uniformly distributed throughout the insulation layer but is selectively placed in specific local regions. The insulation structure has different properties in different locations: air gaps in non-overlapping regions for capacitance reduction, and continuous insulation in overlapping regions for electrical isolation, optimizing both performance and reliability locally

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The air gap effectively reduces parasitic capacitance, preventing electrical shorts and improving the performance and reliability of variable resistance memory devices by maintaining the integrity of the conductive lines and memory units.

Implementation Method 1

As the size of a variable resistance memory device decreases, the parasitic capacitance between conductive lines or memory cells may be problematic

Methodology Applied
Scientific EffectParasitic capacitance: Capacitance

Data Source

PatentUS10546999B2Variable resistance memory devices and methods of manufacturing the same
Publication Date: 2020.01.28 SAMSUNG ELECTRONICS CO LTD
  • US10546999B2 patent drawing
  • US10546999B2 patent drawing
  • US10546999B2 patent drawing

AI summary

A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the first conductive lines nor the second conductive lines in the third direction.