Variable Resistance Memory Devices With Air Gaps
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Solution Overview
Problem
As memory devices become more integrated, the reduced pitch between memory cells leads to interference, and the manufacturing process can alter the properties of the variable resistance layer, affecting the reliability and stability of these devices.
Innovation Solution
The implementation of a variable resistance memory device with air gaps between memory cells, using a low-temperature spin-on hard mask material for sacrificial layer formation, which prevents property fluctuation and ensures structural stability by minimizing parasitic capacitance and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch between memory cells is decreased to increase integration, then device integration is improved, but interference between memory cells increases
Solution Approach 1:
The patent introduces air gaps that physically segment and isolate adjacent memory cells from each other. These air gaps create spatial separation between cells, preventing electrical interference and parasitic capacitance coupling while maintaining high integration density. The segmentation is achieved through sacrificial layer removal that creates voids between neighboring memory cell structures.
Solution Approach 2:
The air gaps act as intermediary regions between memory cells, providing electrical isolation and reducing parasitic capacitance. By introducing this intermediate space filled with air (low dielectric constant), the patent mediates the interaction between adjacent cells, preventing harmful electrical coupling while allowing close proximity for high integration.
2Manufacturing precision
If manufacturing process temperature is increased for material deposition, then material deposition quality is improved, but properties of variable resistance layer are altered
Solution Approach 1:
The patent segments the manufacturing process into distinct temperature zones by using a sacrificial layer that can be deposited at low temperature and subsequently removed. This allows the variable resistance layer to be formed at low temperature preserving its properties, while other structural components can be deposited at higher temperatures for quality, with the sacrificial layer acting as a temporary separator.
Solution Approach 2:
The sacrificial layer is a temporary, disposable structure used during manufacturing that is later removed to create air gaps. This disposable layer enables low-temperature processing of the variable resistance layer without compromising final device quality, as the sacrificial material itself is removed after serving its protective and spacing function.
3Object-affected harmful factors
If air gaps are introduced between memory cells to reduce interference, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent extracts material to create air gaps by removing sacrificial layers from the device structure. This extraction process creates voids between memory cells that reduce parasitic capacitance. The complexity is managed by using a systematic sacrificial layer deposition and removal process that can be integrated into existing manufacturing flows.
Solution Approach 2:
The sacrificial layer is temporarily introduced to define air gap regions, then discarded through removal processes. This temporary structure enables precise air gap formation without requiring complex direct patterning methods. The sacrificial material is discarded after serving its purpose of defining the air gap geometry and providing structural support during processing.
Data Source
AI summary
A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.