Variable Resistance Memory Anti-Fuse Integration
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Solution Overview
Problem
Conventional PRAM devices face challenges in reducing the area of the memory device due to the formation of anti-fuses in peripheral circuit regions, which limits integration density and capacity.
Innovation Solution
The anti-fuse is formed within the cell region instead of the peripheral circuit region, with a U-shaped fourth electrode directly contacting the second selection structure, allowing for a more compact design and higher capacity by skipping elements in the memory unit formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If anti-fuse is formed in peripheral circuit region, then anti-fuse can be formed separately from memory unit, but device area increases and integration density decreases
Solution Approach 1:
The patent merges the anti-fuse formation process with the memory unit formation process. The anti-fuse is formed within the cell region by utilizing the same electrode structures (first electrode, variable resistance pattern, second electrode) that constitute the memory unit, thereby eliminating the need for separate peripheral circuit region and reducing overall device area.
Solution Approach 2:
The electrode structures in the cell region serve dual functions: they form both the memory unit and the anti-fuse. By skipping the formation of certain elements (variable resistance pattern or second electrode) in specific regions, the same structural framework accomplishes both memory storage and anti-fuse protection functions, increasing integration density.
2Ease of manufacture
If anti-fuse is formed in peripheral circuit region, then manufacturing process can be simplified, but integration density and capacity are limited
Solution Approach 1:
The patent combines anti-fuse and memory unit formation into a single integrated process within the cell region. The same electrode layers and structural formation steps are used for both components, eliminating separate manufacturing stages and enabling higher integration density without complicating the manufacturing process.
Solution Approach 2:
The patent employs a skipping strategy where certain elements (variable resistance pattern or second electrode) are intentionally omitted in anti-fuse regions during the memory unit formation process. This allows the anti-fuse to be formed as a byproduct of the memory unit fabrication, achieving high integration density without additional manufacturing complexity.
3Area of stationary object
If fourth electrode extends deeper than second electrode, then anti-fuse can be formed in cell region with compact design, but electrode structure complexity increases
Solution Approach 1:
The patent resolves the area constraint by extending the fourth electrode in the vertical dimension (depth) rather than expanding horizontally. The fourth electrode penetrates deeper into the substrate than the second electrode, allowing the anti-fuse to be formed within the cell region's vertical space, thereby maintaining compact horizontal footprint while accommodating the additional electrode structure.
Data Source
AI summary
A variable resistance memory device includes a memory unit including a first electrode, a variable resistance pattern and a second electrode sequentially stacked on a substrate, a first selection structure on the memory unit, a third electrode structure on the first selection structure, and an anti-fuse including a fourth electrode, a second selection structure and a fifth electrode structure sequentially stacked. The fourth electrode directly contacts the second selection structure, and a bottom of the fourth electrode is lower than a bottom of the second electrode.