Variable Resistance Memory Cell Asymmetric Current Control
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Solution Overview
Problem
The commercialization of cross-point type resistance change memory is hindered by the need to optimize set and reset currents of variable resistance elements to prevent voltage drops and facilitate high-speed data storage, while maintaining current detection capabilities, which is challenging due to practical upper and lower limits of these currents.
Innovation Solution
A nonvolatile semiconductor memory device with memory cells using variable resistance elements where the reset current is significantly smaller than the set current, allowing for efficient operations by controlling voltages and currents to minimize voltage drops and enable batch operations without the need for additional selectors, utilizing a control circuit to manage the transition between high and low resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the set current and reset current are reduced to suppress voltage drop caused by wiring resistance, then voltage drop is suppressed, but current detection becomes difficult due to thermal noise and circuit component noise
Solution Approach 1:
The patent applies parameter changes by utilizing the asymmetric current-voltage characteristics of the variable resistance element. Specifically, it exploits the difference between set current (high current to transition from high resistance to low resistance) and reset current (low current to transition from low resistance to high resistance). By using this asymmetric property, the system can operate at lower currents during read operations while maintaining reliable detection through the distinct current levels during set and reset operations.
2Productivity
If the set current and reset current are made small to enable batch operation of many memory cells, then data storage speed increases, but current detection becomes difficult due to noise
Solution Approach 1:
The patent utilizes parameter changes by leveraging the asymmetric current characteristics of the variable resistance element. The set operation uses a high current to achieve rapid transition from high resistance to low resistance state, while the reset operation uses a low current to transition from low resistance to high resistance state. This asymmetric parameter usage enables batch operations with high data storage speed while maintaining detectable current levels through the inherent current asymmetry of the resistance change mechanism.
3Reliability
If selectors are added to prevent disturbance on peripheral circuits, then circuit isolation improves, but device complexity increases and stacking becomes more difficult
Solution Approach 1:
The patent applies the taking out principle by removing the selector component from the memory cell structure. Instead of using a selector transistor to isolate the variable resistance element from peripheral circuits, the invention relies on the inherent asymmetric current characteristics of the variable resistance element itself to achieve circuit isolation. This extraction of the selector component simplifies the device structure and enables easier stacking while maintaining reliable circuit isolation through the current asymmetry property.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-speed data storage by enabling batch write and read operations with reduced current flow, eliminating the need for selectors and enhancing data storage speed, while maintaining the integrity of current detection, thus overcoming the limitations of conventional memory devices.
Implementation Method 1
a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.