Variable Resistance Memory Device Asymmetric Stacking
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Solution Overview
Problem
Variable resistance memory devices face challenges in operational reliability due to thermal disturbances between upper and lower memory cells, which can be exacerbated by the close proximity of these cells in existing stacked structures.
Innovation Solution
The design incorporates a zigzag pattern or shifting of memory cells to increase physical distances between upper and lower memory cells without increasing the height of metal wirings, utilizing a stacked cross-point cell array structure with conductive lines and memory cells arranged in a specific overlapping pattern to enhance operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked closely in existing stacked structures, then device integration density is improved, but thermal disturbances between upper and lower memory cells increase
Solution Approach 1:
The patent applies asymmetry by shifting the horizontal positions of upper and lower memory cells relative to each other, creating an offset stacked structure. This asymmetric arrangement increases the physical distance between adjacent memory cells in the vertical stack, thereby reducing thermal disturbances while maintaining high integration density through the stacked configuration.
Solution Approach 2:
The patent transitions from a purely vertical stacking approach to a three-dimensional arrangement that incorporates horizontal offset. By introducing horizontal displacement as an additional spatial dimension in the memory cell arrangement, the design achieves both high density and reduced thermal coupling between cells.
2Object-affected harmful factors
If physical distance between upper and lower memory cells is increased, then thermal disturbances are reduced, but device integration density decreases
Solution Approach 1:
The patent implements nesting by stacking multiple memory cells vertically in overlapping regions, creating a multi-layered structure. This allows multiple memory cells to occupy the same horizontal footprint area, achieving high integration density while the vertical separation and horizontal offset reduce thermal interference between nested cells.
Solution Approach 2:
By utilizing the vertical dimension for stacking while incorporating horizontal offset, the patent achieves three-dimensional space utilization that maximizes integration density without compromising thermal isolation. The memory cells are arranged in both vertical and horizontal dimensions to optimize both density and thermal performance.
Data Source
AI summary
A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.