Variable Resistance Memory Device with Auxiliary Source Line
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Solution Overview
Problem
Semiconductor memory devices using variable resistance elements face challenges in reducing the electrical resistance of signal lines, which limits integration density and speed due to increased resistance from down-scaling and contact plug interfacial resistance.
Innovation Solution
The semiconductor memory device design includes forming a variable resistance element with a main source line and bit line at the same layer level, using an auxiliary source line connected to multiple active areas, and forming contact plugs and word lines in a self-align process to reduce signal line resistance and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If down-scaling is applied to increase integration density, then integration density is improved, but electrical resistance of signal lines increases
Solution Approach 1:
The patent forms source lines and bit lines at the same layer level (planar configuration) rather than using vertical stacking, reducing the number of contact plugs needed and minimizing interfacial resistance while maintaining high integration density through lateral arrangement
Solution Approach 2:
The patent removes intermediate contact plugs between source lines and bit lines by forming them at the same layer level, eliminating the interfacial resistance that would be introduced by multiple contact interfaces in vertical configurations
2Adaptability or versatility
If multiple contact plugs are used to connect signal lines, then connectivity is improved, but total resistance of signal lines increases
Solution Approach 1:
The patent merges source lines and bit lines into the same layer level, allowing direct planar connection without intermediate contact plugs, thereby reducing total resistance while maintaining full connectivity between memory cell components
Solution Approach 2:
The patent segments the signal line network into distinct planar layers, with source lines and bit lines formed at the same level but separated by insulation, reducing the need for vertical interconnections and associated contact resistance
Data Source
AI summary
A semiconductor memory device with a variable resistance element includes a plurality of active areas isolated from one another by an isolation layer formed in a substrate, a plurality of word lines crossing over the plurality of active areas, an auxiliary source line disposed between two selected word lines and commonly connected to at least two active areas among the plurality of active areas between the two selected word lines, and a plurality of contact plugs each connected to a corresponding active area.