Variable Resistance Memory Device Using Bipolar Diode Selection

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Solution Overview

Problem

Current variable resistance memory devices face challenges in reducing the size of memory cell arrays while efficiently writing and reading data '1' and '0' without disturbance, as they require complex configurations and multiple conductive lines.

Innovation Solution

The proposed variable resistance memory device incorporates a spin orbit torque (SOT) magnetic tunnel junction device and bipolar selection diodes, utilizing three conductive lines to perform write and read operations, with distinct current paths for each operation to prevent data disturbance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional variable resistance memory devices use multiple conductive lines and complex configurations to write and read data, then data writing and reading can be performed, but the memory cell array size increases and device complexity increases

Engineering Contradiction:
Improvememory cell array sizeVSAvoiddata writing and reading capability
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The patent combines the selection device and the variable resistance memory cell into a single integrated structure. The bipolar diode serves as both the selection device and is directly integrated with the memory cell, eliminating the need for separate selection transistors and reducing the number of conductive lines required. This merging reduces the memory cell array size while maintaining data writing and reading capabilities through the diode's inherent selection properties.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bipolar diode performs multiple functions: it acts as a selection device for accessing memory cells, provides current direction control for write operations, and enables read operations through its rectifying properties. This multi-functionality eliminates the need for separate selection devices and reduces device complexity while maintaining full data writing and reading functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If conventional memory devices use separate current paths for write and read operations, then data disturbance is prevented, but device complexity and size increase

Engineering Contradiction:
Improveread operation disturbance preventionVSAvoidcurrent path configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the write and read current paths by using the same bipolar diode and conductive lines for both operations. The diode's inherent rectifying properties naturally direct current flow: during write operations, current flows in one direction to switch the memory cell state, while during read operations, current flows in the opposite direction to sense the state without causing disturbance. This unified approach prevents read disturbance while simplifying the current path configuration.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If memory devices use complex configurations to reduce memory cell array size, then storage density improves, but manufacturing complexity increases

Engineering Contradiction:
Improvememory cell array areaVSAvoiddevice fabrication
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The bipolar diode and memory cell are fabricated as a single integrated structure using standard semiconductor processing techniques. The diode is formed directly adjacent to and integrated with the variable resistance memory cell, sharing common conductive lines and interconnect structures. This merged configuration reduces the memory cell array area while maintaining manufacturability through conventional fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for a compact memory cell array that can easily write and read data '1' and '0' with reduced size and minimized read operation disturbances, enhancing data storage efficiency.

Implementation Method 1

each of the plurality of variable resistance layers including a spin orbit torque magnetic tunnel junction device

Methodology Applied
Scientific EffectSpin orbit torque:

Implementation Method 2

each of the plurality of bipolar selection devices including a bipolar diode

Methodology Applied
Scientific EffectBipolar diode rectification: Diode

Data Source

PatentUS11522015B2Variable resistance memory device
Publication Date: 2022.12.06 SAMSUNG ELECTRONICS CO LTD
  • US11522015B2 patent drawing
  • US11522015B2 patent drawing
  • US11522015B2 patent drawing

AI summary

A variable resistance memory device includes a first conductive line, a bipolar selection device on the first conductive line and electrically connected to the first conductive line, a second conductive line on the first conductive line and electrically connected to the bipolar selection device, a variable resistance layer on the second conductive line and electrically connected to the second conductive line, and a third conductive line on the variable resistance layer and electrically connected to the variable resistance layer.