Variable Resistance Memory Bit Line Configuration
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Solution Overview
Problem
Variable resistance memory devices face challenges with high resistance in interconnect lines and complex circuit configurations due to parasitic resistance and the need for source lines.
Innovation Solution
The design eliminates the need for source lines by using bit lines in a memory cell array, where a first bit line is connected to a resistance sensing element and a second bit line adjacent to it is connected to a switching device, allowing current to flow through both bit lines, reducing parasitic resistances and simplifying the circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source lines are used in the memory cell array, then the circuit configuration is complete and functional, but the circuit complexity increases and parasitic resistance increases
Solution Approach 1:
The patent removes the source line from the memory cell array, extracting the problematic component that caused both circuit complexity and parasitic resistance issues. The source line is completely eliminated from the structure, and its function is replaced by using bit lines in a different configuration where bit lines are connected to both resistance sensing elements and switching devices, allowing the circuit to function without the traditional source line.
Solution Approach 2:
The bit line is given multiple functions: it serves as both a signal line for selecting memory cells and as a current path replacement for the source line. By connecting bit lines to both resistance sensing elements and switching devices, the bit line performs the dual role of traditional bit lines and source lines, simplifying the overall circuit configuration while maintaining functionality.
2Reliability
If source lines are used in the memory cell array, then the circuit is complete, but the parasitic resistance increases
Solution Approach 1:
The source line is completely removed from the memory cell array structure, eliminating the parasitic resistance associated with source line connections. This extraction of the harmful component directly reduces the overall parasitic resistance in the memory device while maintaining circuit functionality through the alternative bit line configuration.
3Reliability
If conventional interconnect lines are used, then the memory cell can be electrically connected, but the line resistance is undesirably high
Solution Approach 1:
The patent merges the functions of bit lines and source lines into a unified bit line structure. By connecting bit lines to both resistance sensing elements and switching devices, the design eliminates the need for separate source line interconnects, thereby reducing the total length and number of interconnect lines, which directly reduces line resistance and improves electrical connection quality.
Data Source
AI summary
Variable resistance memory devices are provided. A variable resistance memory device includes a memory cell that includes a switching device and a resistance sensing element that is connected in series with the switching device. The variable resistance memory device includes a word line that extends in a first direction and that is connected to a gate of the switching device. Moreover, the variable resistance memory device includes a plurality of bit lines extending in a second direction. A first connection node of a first bit line among the plurality of bit lines is electrically connected to the resistance sensing element. A second connection node of a second bit line, among the plurality of bit lines, adjacent the first bit line is electrically connected to the switching device.